Searched defs:Reg (Results 51 - 75 of 253) sorted by relevance

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/external/llvm/include/llvm/Target/
H A DTargetFrameLowering.h42 unsigned Reg; member in struct:llvm::TargetFrameLowering::SpillSlot
/external/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { argument
62 unsigned Node = GroupNodeIndices[Reg];
74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
76 Regs.push_back(Reg);
83 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) argument
107 IsLive(unsigned Reg) argument
161 unsigned Reg = *AI; local
174 unsigned Reg = *I; local
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H A DCriticalAntiDepBreaker.cpp67 unsigned Reg = *AI; local
68 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
69 KillIndices[Reg] = BBSize;
70 DefIndices[Reg] = ~0u;
82 unsigned Reg = *AI; local
83 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
84 KillIndices[Reg] = BBSize;
85 DefIndices[Reg] = ~0u;
108 for (unsigned Reg = 0; Reg !
180 unsigned Reg = MO.getReg(); local
266 unsigned Reg = MO.getReg(); local
303 unsigned Reg = MO.getReg(); local
624 unsigned Reg = MO.getReg(); local
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H A DLiveRangeEdit.cpp161 void LiveRangeEdit::eraseVirtReg(unsigned Reg) { argument
162 if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
163 LIS.removeInterval(Reg);
256 unsigned Reg = MOI->getReg(); local
257 if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
259 if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
262 for (MCRegUnitIterator Units(Reg, MRI.getTargetRegisterInfo());
272 LiveInterval &LI = LIS.getInterval(Reg);
278 if (MI->readsVirtualRegister(Reg)
323 unsigned Reg = RegsToErase[i]; local
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H A DMachineInstrBundle.cpp133 unsigned Reg = MO.getReg(); local
134 if (!Reg)
136 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
137 if (LocalDefSet.count(Reg)) {
141 KilledDefSet.insert(Reg);
143 if (ExternUseSet.insert(Reg)) {
144 ExternUses.push_back(Reg);
146 UndefUseSet.insert(Reg);
150 KilledUseSet.insert(Reg);
156 unsigned Reg local
187 unsigned Reg = LocalDefs[i]; local
197 unsigned Reg = ExternUses[i]; local
252 analyzeVirtReg(unsigned Reg, SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) argument
281 analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI) argument
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H A DMachineRegisterInfo.cpp46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument
48 VRegInfo[Reg].first = RC;
52 MachineRegisterInfo::constrainRegClass(unsigned Reg, argument
55 const TargetRegisterClass *OldRC = getRegClass(Reg);
64 setRegClass(Reg, NewRC);
69 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { argument
71 const TargetRegisterClass *OldRC = getRegClass(Reg);
80 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
89 setRegClass(Reg, NewRC);
103 unsigned Reg local
116 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
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H A DRegisterScavenging.cpp34 void RegScavenger::setUsed(unsigned Reg) { argument
35 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
40 bool RegScavenger::isAliasUsed(unsigned Reg) const {
41 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
42 if (isUsed(*AI, *AI == Reg))
50 I->Reg = 0;
107 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { argument
108 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
133 unsigned Reg = MO.getReg(); local
134 if (!Reg || TargetRegisterInf
205 unsigned Reg = MO.getReg(); local
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H A DStackMaps.cpp89 unsigned Reg = (++MOI)->getReg(); local
91 Locs.push_back(Location(StackMaps::Location::Direct, Size, Reg, Imm));
97 unsigned Reg = (++MOI)->getReg(); local
99 Locs.push_back(Location(StackMaps::Location::Indirect, Size, Reg, Imm));
139 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) { argument
140 int RegNo = TRI->getDwarfRegNum(Reg, false);
141 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNo < 0; ++SR)
148 /// Create a live-out register record for the given register Reg.
150 StackMaps::createLiveOutReg(unsigned Reg, const TargetRegisterInfo *TRI) const { argument
151 unsigned RegNo = getDwarfRegNum(Reg, TR
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H A DTargetRegisterInfo.cpp37 if (!Reg)
39 else if (TargetRegisterInfo::isStackSlot(Reg))
40 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
41 else if (TargetRegisterInfo::isVirtualRegister(Reg))
42 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
43 else if (TRI && Reg < TRI->getNumRegs())
44 OS << '%' << TRI->getName(Reg);
46 OS << "%physreg" << Reg; local
H A DTargetSchedule.cpp269 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg(); local
272 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
H A DVirtRegMap.cpp122 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
123 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
124 OS << '[' << PrintReg(Reg, TRI) << " -> "
125 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
126 << MRI->getRegClass(Reg)->getName() << "\n";
131 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
132 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
133 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
134 << "] " << MRI->getRegClass(Reg)
416 unsigned Reg = *I; local
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/external/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinterDwarf.cpp59 OutStreamer.AddComment("DW_CFA_offset + Reg (" +
190 static void emitDwarfRegOp(ByteStreamer &Streamer, int Reg) { argument
191 assert(Reg >= 0);
192 if (Reg < 32) {
193 Streamer.EmitInt8(dwarf::DW_OP_reg0 + Reg,
194 dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
197 Streamer.EmitULEB128(Reg, Twine(Reg));
202 static void emitDwarfRegOpIndirect(ByteStreamer &Streamer, int Reg, int Offset, argument
204 assert(Reg >
253 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false); local
335 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false); local
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp199 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); local
200 if (TargetRegisterInfo::isVirtualRegister(Reg))
201 return Reg;
248 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); local
249 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
250 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
252 VRBase = Reg;
823 unsigned Reg = II.getImplicitDefs()[i - NumDefs];
827 UsedRegs.push_back(Reg);
828 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMa
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H A DScheduleDAGSDNodes.cpp118 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); local
119 if (TargetRegisterInfo::isVirtualRegister(Reg))
126 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
127 PhysReg = Reg;
129 TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo));
641 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
642 if (TargetRegisterInfo::isVirtualRegister(Reg))
768 unsigned Reg = 0;
773 Reg = II->getReg();
777 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
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/external/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp100 static bool isGPR64(unsigned Reg, unsigned SubReg, argument
104 if (TargetRegisterInfo::isVirtualRegister(Reg))
105 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
106 return AArch64::GPR64RegClass.contains(Reg);
109 static bool isFPR64(unsigned Reg, unsigned SubReg, argument
111 if (TargetRegisterInfo::isVirtualRegister(Reg))
112 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
114 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
117 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
118 (AArch64::FPR128RegClass.contains(Reg)
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/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp250 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); local
251 MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
H A DARMTargetStreamer.cpp51 void ARMTargetStreamer::emitMovSP(unsigned Reg, int64_t Offset) {} argument
/external/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.cpp141 unsigned Reg = CSI[i].getReg(); local
143 switch (Reg) {
158 if (Reg == FramePtr)
203 unsigned Reg = I->getReg(); local
205 switch (Reg) {
224 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
427 unsigned Reg = CSI[i-1].getReg(); local
433 if (Reg == ARM::LR) {
436 MF.getRegInfo().isLiveIn(Reg))
441 MBB.addLiveIn(Reg);
468 unsigned Reg = CSI[i-1].getReg(); local
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H A DThumb2ITBlockPass.cpp67 unsigned Reg = MO.getReg(); local
68 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
71 LocalUses.push_back(Reg);
73 LocalDefs.push_back(Reg);
77 unsigned Reg = LocalUses[i]; local
78 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
84 unsigned Reg = LocalDefs[i]; local
85 for (MCSubRegIterator Subreg(Reg, TR
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/external/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp212 unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) { argument
213 MCSuperRegIterator SRI(Reg, TRI);
242 unsigned Reg = CSI[i].getReg(); local
247 unsigned SuperReg = uniqueSuperReg(Reg, TRI);
266 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
267 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RC,
269 MBB.addLiveIn(Reg);
297 unsigned Reg = CSI[i].getReg(); local
302 unsigned SuperReg = uniqueSuperReg(Reg, TRI);
320 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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/external/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp44 SDValue Reg; member in struct:__anon26028::MSP430ISelAddressMode::__anon26030
67 if (BaseType == RegBase && Base.Reg.getNode() != nullptr) {
68 errs() << "Base.Reg ";
69 Base.Reg.getNode()->dump();
174 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
181 AM.Base.Reg = N;
203 && AM.Base.Reg.getNode() == nullptr) {
258 if (!AM.Base.Reg.getNode())
259 AM.Base.Reg = CurDAG->getRegister(0, VT);
265 AM.Base.Reg;
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/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp249 bool baseRegNeedsLoadStoreMask(unsigned Reg) { argument
251 return Reg != Mips::SP && Reg != Mips::T8;
/external/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp80 /// and the underlying object in Reg and Val respectively, if the function's
82 bool isCallViaRegister(MachineInstr &MI, unsigned &Reg,
94 void incCntAndSetReg(ValueType Entry, unsigned Reg);
117 /// Return type of register Reg.
118 static MVT::SimpleValueType getRegTy(unsigned Reg, MachineFunction &MF) { argument
119 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
148 unsigned Reg = Ty == MVT::i32 ? Mips::GP : Mips::GP_64; local
152 if (MO.isReg() && MO.getReg() == Reg) {
214 unsigned Reg; local
218 if (!isCallViaRegister(*I, Reg, Entr
246 isCallViaRegister(MachineInstr &MI, unsigned &Reg, ValueType &Val) const argument
288 unsigned Reg = ScopedHT.lookup(Entry).second; local
293 incCntAndSetReg(ValueType Entry, unsigned Reg) argument
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp81 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1; local
83 MCCFIInstruction::createDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0);
/external/llvm/lib/Target/R600/
H A DR600InstrInfo.cpp315 unsigned Reg = MO.getReg(); local
316 if (Reg == AMDGPU::ALU_CONST) {
338 unsigned Reg = MI->getOperand(SrcIdx).getReg();
339 if (Reg == AMDGPU::ALU_CONST) {
345 if (Reg == AMDGPU::ALU_LITERAL_X) {
366 unsigned Reg = Srcs[i].first->getReg();
367 unsigned Index = RI.getEncodingValue(Reg) & 0xff;
368 if (Reg == AMDGPU::OQAP) {
371 if (PV.find(Reg) != PV.end()) {
381 unsigned Chan = RI.getHWRegChan(Reg);
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