Searched defs:N1 (Results 76 - 96 of 96) sorted by path

1234

/external/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h1305 ShuffleVectorSDNode(EVT VT, unsigned Order, DebugLoc dl, SDValue N1, argument
1308 InitOperands(Ops, N1, N2);
/external/llvm/lib/Analysis/
H A DDependenceAnalysis.cpp1895 // 0 <= i <= N1 and some 0 <= j <= N2, where N1 and N2 are the (normalized)
1906 // a1*0 - a2*N2 <= c2 - c1 <= a1*N1 - a2*0
1907 // -a2*N2 <= c2 - c1 <= a1*N1
1910 // a1*0 - a2*0 <= c2 - c1 <= a1*N1 - a2*N2
1911 // 0 <= c2 - c1 <= a1*N1 - a2*N2
1914 // a1*N1 - a2*N2 <= c2 - c1 <= a1*0 - a2*0
1915 // a1*N1 - a2*N2 <= c2 - c1 <= 0
1918 // a1*N1 - a2*0 <= c2 - c1 <= a1*0 - a2*N2
1919 // a1*N1 <
1935 const SCEV *N1 = collectUpperBound(Loop1, A1->getType()); local
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp291 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
292 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
295 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
308 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
310 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
619 SDValue N0, N1, N2; local
620 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
673 SDValue N0, SDValue N1) {
677 if (SDNode *R = isConstantBuildVectorOrConstantInt(N1)) {
687 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
672 ReassociateOps(unsigned Opc, SDLoc DL, SDValue N0, SDValue N1) argument
927 SDValue N1 = Op.getOperand(1); local
1328 SDValue N1 = N->getOperand(1); local
1460 combineShlAddConstant(SDLoc DL, SDValue N0, SDValue N1, SelectionDAG &DAG) argument
1483 SDValue N1 = N->getOperand(1); local
1655 SDValue N1 = N->getOperand(1); local
1696 SDValue N1 = N->getOperand(1); local
1727 SDValue N1 = N->getOperand(1); local
1820 SDValue N1 = N->getOperand(1); local
1853 SDValue N1 = N->getOperand(1); local
1865 SDValue N1 = N->getOperand(1); local
1985 SDValue N1 = N->getOperand(1); local
2070 SDValue N1 = N->getOperand(1); local
2122 SDValue N1 = N->getOperand(1); local
2164 SDValue N1 = N->getOperand(1); local
2217 SDValue N1 = N->getOperand(1); local
2255 SDValue N1 = N->getOperand(1); local
2442 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); local
2592 SDValue N1 = N->getOperand(1); local
2981 MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, bool DemandHighBits) argument
3158 MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) argument
3230 SDValue N1 = N->getOperand(1); local
3697 SDValue N1 = N->getOperand(1); local
3946 SDValue N1 = N->getOperand(1); local
4115 SDValue N1 = N->getOperand(1); local
4261 SDValue N1 = N->getOperand(1); local
4506 SDValue N1 = N->getOperand(1); local
4664 SDValue N1 = N->getOperand(1); local
4750 SDValue N1 = N->getOperand(1); local
5830 SDValue N1 = N->getOperand(1); local
6465 SDValue N1 = N->getOperand(1); local
6675 SDValue N1 = N->getOperand(1); local
6766 SDValue N1 = N->getOperand(1); local
6830 SDValue N1 = N->getOperand(1); local
6905 SDValue N1 = N->getOperand(1); local
6959 SDValue N1 = N->getOperand(1); local
6973 SDValue N1 = N->getOperand(1); local
7140 SDValue N1 = N->getOperand(1); local
7361 SDValue N1 = N->getOperand(1); local
10384 SDValue N1 = N->getOperand(1); local
10522 SDValue N1 = N->getOperand(1); local
10572 SDValue N1 = N->getOperand(1); local
10962 SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2) argument
11107 SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, bool NotExtCompare) argument
11398 SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, SDLoc DL, bool foldBooleans) argument
[all...]
H A DLegalizeDAG.cpp96 SDValue N1, SDValue N2,
190 SDValue N1, SDValue N2,
199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
213 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
189 ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl, SDValue N1, SDValue N2, ArrayRef<int> Mask) const argument
H A DSelectionDAG.cpp960 SDVTList VTs, SDValue N1,
965 Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2);
974 BinarySDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2);
1465 // commuteShuffle - swaps the values of N1 and N2, and swaps all indices in
1466 // the shuffle mask M that point at N1 to point at N2, and indices that point
1467 // N2 to point at N1.
1468 static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) { argument
1469 std::swap(N1, N2);
1479 SDValue SelectionDAG::getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, argument
1481 assert(VT == N1
959 GetBinarySDNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1, SDValue N2, bool nuw, bool nsw, bool exact) argument
1790 FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, SDLoc dl) argument
3067 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, bool nuw, bool nsw, bool exact) argument
3536 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3) argument
3643 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4) argument
3650 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) argument
5088 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, SDValue N1) argument
5094 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, SDValue N1, SDValue N2) argument
5100 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3) argument
5106 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4) argument
5113 getNode(unsigned Opcode, SDLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) argument
[all...]
H A DTargetLowering.cpp1206 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, argument
1231 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1233 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1505 return DAG.getSetCC(dl, VT, Val, N1,
1570 DAG.getConstant(C, N1.getValueType()),
1585 DAG.getConstant(C, N1.getValueType()),
1601 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1604 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1624 DAG.getConstant(0, N1.getValueType()),
1632 N1
2015 SDValue N1 = N->getOperand(0); local
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp6329 SDValue N1 = N->getOperand(1); local
6335 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6336 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6337 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6530 SDValue N1 = N->getOperand(1);
6531 if (N1.getOpcode() != ISD::AND)
6541 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
6558 N0->getOperand(1 - i), N1->getOperand(1 - j));
/external/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp347 SDValue N1 = N->getOperand(1); local
349 if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
351 std::swap(N0, N1);
374 SDValue Srl = N1.getOperand(0);
398 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
400 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
401 N1, CurDAG->getConstant(TZ, MVT::i32));
402 CurDAG->UpdateNodeOperands(N, N0, N1);
1039 SDValue N1 = N.getOperand(1); local
2574 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); local
2692 SDValue N1 = N->getOperand(1); local
[all...]
H A DARMISelLowering.cpp4107 /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
4111 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
4119 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0); local
4120 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
4121 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
4162 /// N1 =+[k1 k0 k3 k2 ]
4179 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0); local
4180 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
5788 SDNode *N1 local
5799 SDNode *N1 = N->getOperand(1).getNode(); local
5813 SDNode *N1 = Op.getOperand(1).getNode(); local
5911 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) argument
5954 SDValue N1 = Op.getOperand(1); local
5989 SDValue N1 = Op.getOperand(1); local
7584 SDValue N1 = N->getOperand(1); local
7677 SDValue N1 = N->getOperand(1); local
7693 AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
7936 PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
7959 SDValue N1 = N->getOperand(1); local
7975 SDValue N1 = N->getOperand(1); local
8009 SDValue N1 = N->getOperand(1); local
8380 SDValue N1 = N->getOperand(1); local
9394 SDValue N1 = N->getOperand(1); local
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp443 SDValue N1 = LD->getOperand(1); local
447 if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
448 N1.getNode()->getValueType(0) == MVT::i32) {
510 SDValue N1 = LD->getOperand(1); local
514 if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
515 N1.getNode()->getValueType(0) == MVT::i32) {
931 SDValue N1 = N->getOperand(1); local
932 if (N01 == N1) {
942 N1);
955 SDValue N1 local
1663 SDValue N1 = N.getOperand(1); local
[all...]
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp121 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
356 SDValue N1, SDValue N2,
358 if (N1.getOpcode() == ISD::LOAD &&
359 N1.hasOneUse() &&
360 IsLegalToFold(N1, Op, Op, OptLevel)) {
361 LoadSDNode *LD = cast<LoadSDNode>(N1);
368 MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
374 ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
376 ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
355 SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8, unsigned Opc16) argument
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp449 SDValue N1 = N->getOperand(1); local
455 if (SelectDirectAddr(N1, Addr)) {
483 ? SelectADDRsi64(N1.getNode(), N1, Base, Offset)
484 : SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
512 ? SelectADDRri64(N1.getNode(), N1, Base, Offset)
513 : SelectADDRri(N1.getNode(), N1, Bas
1818 SDValue N1 = N->getOperand(1); local
[all...]
H A DNVPTXISelLowering.cpp2654 /// operands N0 and N1. This is a helper for PerformADDCombine that is
2657 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, argument
2681 N0.getOperand(0), N0.getOperand(1), N1);
2752 N0.getOperand(0), N0.getOperand(1), N1);
2766 SDValue N1 = N->getOperand(1); local
2769 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget,
2775 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
/external/llvm/lib/Target/R600/
H A DAMDGPUISelDAGToDAG.cpp740 SDValue N1 = Addr.getOperand(1); local
741 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
763 // (add N0, N1)
765 SDValue N1 = Addr.getOperand(1); local
767 Offset = N1;
H A DAMDGPUISelLowering.cpp1911 SDValue N1 = N->getOperand(1); local
1914 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
1916 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
1917 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
1918 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
1920 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
1921 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
1943 SDValue N1 local
[all...]
/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2144 SDValue N1 = Node->getOperand(1); local
2153 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2217 SDValue N1 = Node->getOperand(1); local
2232 SDValue Ops[] = {N1, InFlag};
2244 SDValue N1 = Node->getOperand(1); local
2296 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2301 std::swap(N0, N1);
2310 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2327 ReplaceUses(N1.getValue(1), Chain);
2329 SDValue Ops[] = { N1, InFla
2392 SDValue N1 = Node->getOperand(1); local
2564 SDValue N1 = Node->getOperand(1); local
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp606 SDValue N1 = Op.getOperand(1); local
611 OtherOp = N1;
612 } else if (N1.getOpcode() == ISD::ADD) {
613 AddOp = N1;
1655 SDValue N1 = N->getOperand(1); local
1658 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1663 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1692 SDValue N1 = N->getOperand(1); local
1695 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1731 SDValue N1 local
[all...]
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineMulDivRem.cpp551 Value *N1 = dyn_castFNegVal(Opnd1, IgnoreZeroSign); local
554 if (N1) {
555 Value *FMul = Builder->CreateFMul(N0, N1);
1246 Constant *N1 = Constant::getAllOnesValue(I.getType()); local
1247 Value *Add = Builder->CreateAdd(Op1, N1);
/external/llvm/unittests/IR/
H A DMDBuilderTest.cpp86 MDNode *N1 = MDHelper.createTBAANode("edoN", R); local
90 EXPECT_NE(N0, N1);
93 EXPECT_GE(N1->getNumOperands(), 2U);
96 EXPECT_TRUE(isa<MDString>(N1->getOperand(0)));
99 EXPECT_EQ(cast<MDString>(N1->getOperand(0))->getString(), "edoN");
102 EXPECT_EQ(N1->getOperand(1), R);
/external/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.cpp2157 TreePatternNode *N1 = Nodes[i], *N2 = Nodes[i+1]; local
2158 assert(N1->getNumTypes() == 1 && N2->getNumTypes() == 1 &&
2161 MadeChange |= N1->UpdateNodeType(0, N2->getExtType(0), *this);
2162 MadeChange |= N2->UpdateNodeType(0, N1->getExtType(0), *this);
2589 const TreePatternNode *N1 = N->getChild(1); local
2590 if (N1->isLeaf())
2592 if (N1->getNumChildren() != 1 || !N1->getChild(0)->isLeaf())
2595 const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N1->getOperator());
/external/valgrind/main/memcheck/tests/
H A Dlong_namespace_xml.cpp17 #define N1 abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz macro
32 namespace N1 { namespace
44 N1::N2::f();

Completed in 668 milliseconds

1234