/external/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 254 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { argument 267 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); 272 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, argument 282 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); 360 unsigned Op1, Op2; local 361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 373 unsigned Op1, Op2; local 374 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 379 DecodeGRRegsRegisterClass(Inst, Op2, Addres 386 unsigned Op1, Op2; local 399 unsigned Op1, Op2; local 413 unsigned Op1, Op2; local 426 unsigned Op1, Op2; local 439 unsigned Op1, Op2; local 524 unsigned Op1, Op2; local 538 unsigned Op1, Op2; local 552 unsigned Op1, Op2, Op3; local 565 unsigned Op1, Op2, Op3; local 578 unsigned Op1, Op2, Op3; local 591 unsigned Op1, Op2, Op3; local 604 unsigned Op1, Op2, Op3; local 618 unsigned Op1, Op2, Op3; local 633 unsigned Op1, Op2, Op3; local 647 unsigned Op1, Op2, Op3; local 661 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local 695 unsigned Op1, Op2, Op3, Op4, Op5; local 715 unsigned Op1, Op2, Op3; local 734 unsigned Op1, Op2, Op3; local [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreSelectionDAGInfo.h | 31 SDValue Op1, SDValue Op2,
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/external/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2, 76 SDValue Op1, SDValue Op2, 92 SDValue Op1, SDValue Op2, 106 SDValue Op1, SDValue Op2, 147 SDValue Op1, SDValue Op2, 57 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 74 EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 90 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument 104 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument 145 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
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/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 54 SDValue Op1, SDValue Op2,
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 833 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 839 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
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H A D | SelectionDAG.h | 606 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, argument 612 Ops.push_back(Op2); 855 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2); 856 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 858 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 860 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 871 SDValue Op1, SDValue Op2); 873 SDValue Op1, SDValue Op2, SDValue Op3); 886 EVT VT2, SDValue Op1, SDValue Op2); 888 EVT VT2, SDValue Op1, SDValue Op2, SDValu [all...] |
H A D | FastISel.h | 280 unsigned Op2, bool Op2IsKill);
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.cpp | 72 const MCOperand &Op2 = MI->getOperand(2); local 77 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { 113 if (Op2.isImm() && Op3.isImm()) { 116 int64_t immr = Op2.getImm(); 147 if (Op2.getImm() > Op3.getImm()) { 150 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; 158 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; 165 const MCOperand &Op2 local 678 const MCOperand &Op2 = MI->getOperand(3); local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 672 SDValue Op2 = Op.getOperand(2); local 675 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); 708 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); 715 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); 716 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); 849 SDValue Op2 = Op.getOperand(2); local 877 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); [all...] |
H A D | SelectionDAG.cpp | 302 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, argument 304 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 308 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 326 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, argument 328 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 333 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 812 SDValue Op1, SDValue Op2, 817 SDValue Ops[] = { Op1, Op2 }; 5234 SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) { argument 5238 if (Op1 == N->getOperand(0) && Op2 811 FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2, void *&InsertPos) argument 5263 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) argument 5269 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) argument 5276 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) argument 5347 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2) argument 5355 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 5403 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument 5411 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 5420 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument 5566 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2) argument 5574 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 5603 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument 5611 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 5628 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) argument 5637 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument [all...] |
H A D | SelectionDAGBuilder.cpp | 2775 SDValue Op2 = getValue(I.getOperand(1)); 2777 Op2.getValueType(), Op2)); 2786 SDValue Op2 = getValue(I.getOperand(1)); 2801 Op1, Op2, nuw, nsw, exact); 2807 SDValue Op2 = getValue(I.getOperand(1)); 2809 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType()); 2812 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2814 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2819 Op2 [all...] |
H A D | FastISel.cpp | 1401 unsigned Op2, bool Op2IsKill) { 1407 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); 1413 .addReg(Op2, Op2IsKill * RegState::Kill); 1418 .addReg(Op2, Op2IsKill * RegState::Kill); 1397 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
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H A D | LegalizeIntegerTypes.cpp | 185 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); local 189 Op2, N->getMemOperand(), N->getOrdering(), 220 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); local 223 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other); 226 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(), 893 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); local 895 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(), 1468 unsigned Op1, Op2; local 1471 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1473 case ISD::SRA: Op1 = ISD::SRL; Op2 [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 172 ICToken Op2 = OperandStack.pop_back_val(); local 179 Val = Op1.second + Op2.second; 183 Val = Op1.second - Op2.second; 187 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 189 Val = Op1.second * Op2.second; 193 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 195 assert (Op2.second != 0 && "Division by zero!"); 196 Val = Op1.second / Op2.second; 200 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 202 Val = Op1.second | Op2 810 doSrcDstMatch(X86Operand &Op1, X86Operand &Op2) argument 2092 X86Operand &Op2 = (X86Operand &)*Operands[2]; local 2118 X86Operand &Op2 = (X86Operand &)*Operands[2]; local [all...] |
/external/llvm/lib/Analysis/ |
H A D | ConstantFolding.cpp | 1615 if (ConstantFP *Op2 = dyn_cast<ConstantFP>(Operands[1])) { 1616 if (Op2->getType() != Op1->getType()) 1619 double Op2V = getValueAsDouble(Op2); 1625 APFloat V2 = Op2->getValueAPF(); 1655 if (ConstantInt *Op2 = dyn_cast<ConstantInt>(Operands[1])) { 1669 Res = Op1->getValue().sadd_ov(Op2->getValue(), Overflow); 1672 Res = Op1->getValue().uadd_ov(Op2->getValue(), Overflow); 1675 Res = Op1->getValue().ssub_ov(Op2->getValue(), Overflow); 1678 Res = Op1->getValue().usub_ov(Op2->getValue(), Overflow); 1681 Res = Op1->getValue().smul_ov(Op2 [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | LoopRerollPass.cpp | 953 Value *Op2 = J2->getOperand(j); local 959 if (Instruction *Op2I = dyn_cast<Instruction>(Op2)) 963 DenseMap<Value *, Value *>::iterator BMI = BaseMap.find(Op2); 965 Op2 = BMI->second; 967 (Instruction*) Op2) != Roots[i].end()) 968 Op2 = IV; 970 if (J1->getOperand(Swapped ? unsigned(!j) : j) != Op2) { 977 J1->getOperand(!j) == Op2) {
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H A D | Scalarizer.cpp | 391 Scatterer Op2 = scatter(&SI, SI.getOperand(2)); local 393 assert(Op2.size() == NumElems && "Mismatched select"); 401 Res[I] = Builder.CreateSelect(Op0[I], Op1[I], Op2[I], 406 Res[I] = Builder.CreateSelect(Op0, Op1[I], Op2[I],
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/external/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.cpp | 804 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; local 809 Ops[4].getAsInteger(10, Op2); 810 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 849 uint32_t Op2 = Bits & 0x7; local 862 + "_c" + utostr(CRm) + "_" + utostr(Op2);
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/external/llvm/include/llvm/Analysis/ |
H A D | ScalarEvolution.h | 607 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 612 Ops.push_back(Op2); 625 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 630 Ops.push_back(Op2);
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/external/llvm/include/llvm/Transforms/Utils/ |
H A D | BuildLibCalls.h | 88 /// 'Op2' and return one value with the same type. If 'Op1/Op2' are long 89 /// double, 'l' is added as the suffix of name, if 'Op1/Op2' are float, we 91 Value *EmitBinaryFloatFnCall(Value *Op1, Value *Op2, StringRef Name,
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 300 MachineOperand Op2 = MI->getOperand(S2); local 301 ChangeOpInto(MI->getOperand(S1), Op2);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 1355 Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1); local 1366 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 && 1381 SDValue Ops[] = { Op1, Op2, DMV }; 1593 SDNode *Op2 = User->getOperand(2).getNode(); 1594 if (!Op2->isMachineOpcode()) 1597 if (Op2->getMachineOpcode() != PPC::LI && 1598 Op2->getMachineOpcode() != PPC::LI8) 1601 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
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/external/llvm/lib/Transforms/Utils/ |
H A D | BuildLibCalls.cpp | 326 /// (e.g. 'fmin'). This function is known to take type matching 'Op1' and 'Op2' 327 /// and return one value with the same type. If 'Op1/Op2' are long double, 'l' 328 /// is added as the suffix of name, if 'Op1/Op2' is a float, we add a 'f' 330 Value *llvm::EmitBinaryFloatFnCall(Value *Op1, Value *Op2, StringRef Name, argument 337 Op1->getType(), Op2->getType(), NULL); 338 CallInst *CI = B.CreateCall2(Callee, Op1, Op2, Name);
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H A D | SimplifyLibCalls.cpp | 1242 Value *Op1 = CI->getArgOperand(0), *Op2 = CI->getArgOperand(1); 1251 return EmitUnaryFloatFnCall(Op2, "exp2", B, Callee->getAttributes()); 1256 return EmitUnaryFloatFnCall(Op2, TLI->getName(LibFunc::exp10), B, 1260 ConstantFP *Op2C = dyn_cast<ConstantFP>(Op2); 1267 hasUnaryFloatFn(TLI, Op2->getType(), LibFunc::sqrt, LibFunc::sqrtf, 1269 hasUnaryFloatFn(TLI, Op2->getType(), LibFunc::fabs, LibFunc::fabsf,
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/external/llvm/lib/AsmParser/ |
H A D | LLParser.cpp | 3608 BasicBlock *Op1, *Op2; 3622 ParseTypeAndBasicBlock(Op2, Loc2, PFS)) 3625 Inst = BranchInst::Create(Op1, Op2, Op0); 3943 Value *Op0, *Op1, *Op2; 3948 ParseTypeAndValue(Op2, PFS)) 3951 if (const char *Reason = SelectInst::areInvalidOperands(Op0, Op1, Op2)) 3954 Inst = SelectInst::Create(Op0, Op1, Op2); 3997 Value *Op0, *Op1, *Op2; 4002 ParseTypeAndValue(Op2, PFS)) 4005 if (!InsertElementInst::isValidOperands(Op0, Op1, Op2)) [all...] |