Searched refs:RegUnit (Results 1 - 10 of 10) sorted by relevance

/external/llvm/lib/CodeGen/
H A DLiveRegMatrix.cpp134 unsigned RegUnit) {
135 LiveIntervalUnion::Query &Q = Queries[RegUnit];
136 Q.init(UserTag, &VirtReg, &Matrix[RegUnit]);
133 query(LiveInterval &VirtReg, unsigned RegUnit) argument
H A DRegisterPressure.cpp304 static bool containsReg(ArrayRef<unsigned> RegUnits, unsigned RegUnit) { argument
305 return std::find(RegUnits.begin(), RegUnits.end(), RegUnit) != RegUnits.end();
385 void PressureDiff::addPressureChange(unsigned RegUnit, bool IsDec, argument
387 PSetIterator PSetI = MRI->getPressureSets(RegUnit);
H A DMachineTraceMetrics.cpp685 unsigned RegUnit;
690 unsigned getSparseSetIndex() const { return RegUnit; }
692 LiveRegUnit(unsigned RU) : RegUnit(RU), Cycle(0), MI(nullptr), Op(0) {}
1124 TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle));
1125 DEBUG(dbgs() << ' ' << PrintRegUnit(RI->RegUnit, MTM.TRI)
/external/llvm/include/llvm/CodeGen/
H A DLiveRegMatrix.h138 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned RegUnit);
H A DMachineRegisterInfo.h546 /// virtual register. If RegUnit is physical, it must be a register unit (from
548 PSetIterator getPressureSets(unsigned RegUnit) const;
646 void setRegUnitUsed(unsigned RegUnit) { argument
647 UsedRegUnits.set(RegUnit);
977 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { argument
979 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
980 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
985 PSet = TRI->getRegUnitPressureSets(RegUnit);
986 Weight = TRI->getRegUnitWeight(RegUnit);
1006 getPressureSets(unsigned RegUnit) cons
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H A DRegisterPressure.h151 void addPressureChange(unsigned RegUnit, bool IsDec,
/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h528 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { argument
529 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
530 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
531 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.h403 struct RegUnit { struct in namespace:llvm
404 // Weight assigned to this RegUnit for estimating register pressure.
409 // Each native RegUnit corresponds to one or two root registers. The full
418 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) { function in struct:llvm::RegUnit
468 SmallVector<RegUnit, 8> RegUnits;
482 // class's units and any inferred RegUnit supersets.
604 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
605 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
H A DRegisterInfoEmitter.cpp196 << "getRegUnitWeight(unsigned RegUnit) const {\n"
197 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
203 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
204 assert(RU.Weight < 256 && "RegUnit too heavy");
208 << " return RUWeightTable[RegUnit];\n";
299 << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
300 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
308 << " unsigned SetListStart = RUSetStartTable[RegUnit];\n"
978 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
985 << "unsigned RegUnit) cons
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/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h410 /// hasRegUnit - Returns true if Reg contains RegUnit.
411 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
413 if (*Units == RegUnit)
615 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
634 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;

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