| /drivers/gpu/drm/exynos/ |
| H A D | exynos_dp_core.c | 282 int lane, lane_count, pll_tries, retval; local
284 lane_count = dp->link_train.lane_count;
289 for (lane = 0; lane < lane_count; lane++)
294 exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
298 buf[1] = dp->link_train.lane_count;
305 for (lane = 0; lane < lane_count; lane++)
331 for (lane = 0; lane < lane_count; lane++)
336 lane_count, buf);
349 static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count) argument
362 exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align, int lane_count) argument
459 int lane, lane_count; local
482 int lane, lane_count, retval; local
557 int lane, lane_count, retval; local
642 exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp, u8 *lane_count) argument
[all...] |
| H A D | exynos_dp_core.h | 133 enum link_lane_count_type lane_count; member in struct:video_info
141 u8 lane_count; member in struct:link_train
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| /drivers/gpu/drm/i915/ |
| H A D | intel_dsi_pll.c | 57 int lane_count, bool eotp)
122 bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count;
137 static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) argument
158 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
236 intel_dsi->lane_count);
375 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);
55 dsi_rr_formula(const struct drm_display_mode *mode, int pixel_format, int video_mode_format, int lane_count, bool eotp) argument
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| H A D | intel_dsi.h | 91 unsigned int lane_count; member in struct:intel_dsi
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| H A D | intel_dsi.c | 426 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, argument
430 8 * 100), lane_count);
442 unsigned int lane_count = intel_dsi->lane_count; local
456 hactive = txbyteclkhs(hactive, bpp, lane_count,
458 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
459 hsync = txbyteclkhs(hsync, bpp, lane_count,
461 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
515 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
548 intel_dsi->lane_count,
[all...] |
| H A D | intel_dsi_panel_vbt.c | 281 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
309 (pclk * bits_per_pixel) / intel_dsi->lane_count;
332 bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count;
350 switch (intel_dsi->lane_count) {
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| H A D | intel_dp_mst.c | 40 int lane_count, slots; local
53 lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
55 intel_dp->lane_count = lane_count;
77 intel_link_compute_m_n(bpp, lane_count,
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| H A D | intel_dp.c | 1025 int lane_count, clock; local
1087 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
1090 lane_count);
1118 intel_dp->lane_count = lane_count;
1123 intel_dp->link_bw, intel_dp->lane_count,
1128 intel_link_compute_m_n(bpp, lane_count,
1136 intel_link_compute_m_n(bpp, lane_count,
[all...] |
| H A D | intel_ddi.c | 401 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
923 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
932 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
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| H A D | intel_drv.h | 557 uint8_t lane_count; member in struct:intel_dp
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| /drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_dp.c | 70 uint8_t lane_count; member in struct:cdv_intel_dp
706 int lane_count, clock; local
719 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
721 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count);
725 intel_dp->lane_count = lane_count;
729 intel_dp->link_bw, intel_dp->lane_count,
737 intel_dp->lane_count
799 int lane_count = 4, bpp = 24; local
1152 cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) argument
[all...] |
| H A D | mdfld_dsi_dpi.c | 470 int lane_count = dsi_config->lane_count; local
485 val = lane_count;
506 (8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK);
523 dsi_config->lane_count, dsi_config->bpp);
749 dsi_config->lane_count,
773 int lane_count = dsi_config->lane_count; local
786 /* lane_count = 3 */
787 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count); local
[all...] |
| H A D | mdfld_dsi_output.c | 434 config->lane_count = 4;
436 config->lane_count = 2;
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| H A D | mdfld_dsi_output.h | 260 int lane_count; member in struct:mdfld_dsi_config
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| /drivers/gpu/drm/ |
| H A D | drm_dp_helper.c | 250 int lane_count)
260 for (lane = 0; lane < lane_count; lane++) {
270 int lane_count)
275 for (lane = 0; lane < lane_count; lane++) {
249 drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count) argument
269 drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count) argument
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| /drivers/edac/ |
| H A D | ppc4xx_edac.c | 444 const unsigned int lane_count = 16; local
455 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) {
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| /drivers/gpu/drm/radeon/ |
| H A D | atombios_dp.c | 241 int lane_count,
248 for (lane = 0; lane < lane_count; lane++) {
240 dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], int lane_count, u8 train_set[4]) argument
|