Searched refs:MCID (Results 1 - 25 of 43) sorted by relevance

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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInst.h24 // MCID is set during instruction lowering.
27 const MCInstrDesc *MCID; member in class:llvm::HexagonMCInst
34 MCInst(), MCID(0), packetStart(0), packetEnd(0) {};
36 MCInst(), MCID(&mcid), packetStart(0), packetEnd(0) {};
50 void setDesc(const MCInstrDesc& mcid) { MCID = &mcid; };
51 const MCInstrDesc& getDesc(void) const { return *MCID; };
H A DHexagonMCInst.cpp33 const uint64_t F = MCID->TSFlags;
40 return (!MCID->isPseudo() &&
52 const uint64_t F = MCID->TSFlags;
58 const uint64_t F = MCID->TSFlags;
64 const uint64_t F = MCID->TSFlags;
70 const uint64_t F = MCID->TSFlags;
118 const uint64_t F = MCID->TSFlags;
124 const uint64_t F = MCID->TSFlags;
130 const uint64_t F = MCID->TSFlags;
136 const uint64_t F = MCID
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/external/llvm/include/llvm/MC/
H A DMCInstrDesc.h98 namespace MCID { namespace in namespace:llvm
191 return Flags & (1 << MCID::Variadic);
197 return Flags & (1 << MCID::HasOptionalDef);
204 return Flags & (1 << MCID::Pseudo);
209 return Flags & (1 << MCID::Return);
214 return Flags & (1 << MCID::Call);
221 return Flags & (1 << MCID::Barrier);
231 return Flags & (1 << MCID::Terminator);
239 return Flags & (1 << MCID::Branch);
245 return Flags & (1 << MCID
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/external/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); local
23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
26 unsigned Opcode = MCID.getOpcode();
43 const MCInstrDesc &MCID = MI->getDesc(); local
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
H A DARMCodeEmitter.cpp101 const MCInstrDesc &MCID,
107 const MCInstrDesc &MCID) const;
279 const MCInstrDesc &MCID = MI.getDesc(); local
282 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ?
485 const MCInstrDesc &MCID = MI.getDesc(); local
487 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
821 const MCInstrDesc &MCID = MI.getDesc(); local
829 Binary |= getAddrModeSBit(MI, MCID);
848 const MCInstrDesc &MCID = MI.getDesc(); local
857 Binary |= getAddrModeSBit(MI, MCID);
1014 getMachineSoRegOpValue(const MachineInstr &MI, const MCInstrDesc &MCID, const MachineOperand &MO, unsigned OpIdx) argument
1097 const MCInstrDesc &MCID = MI.getDesc(); local
1200 const MCInstrDesc &MCID = MI.getDesc(); local
1284 const MCInstrDesc &MCID = MI.getDesc(); local
1369 const MCInstrDesc &MCID = MI.getDesc(); local
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H A DThumb2SizeReduction.cpp203 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { argument
204 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
523 const MCInstrDesc &MCID = MI->getDesc(); local
524 if (MCID.hasOptionalDef() &&
525 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
673 const MCInstrDesc &MCID = MI->getDesc(); local
674 if (MCID.hasOptionalDef()) {
675 unsigned NumOps = MCID.getNumOperands();
701 unsigned NumOps = MCID.getNumOperands();
703 if (i < NumOps && MCID
738 const MCInstrDesc &MCID = MI->getDesc(); local
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H A DMLxExpansionPass.cpp186 const MCInstrDesc &MCID = MI->getDesc(); local
187 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
190 unsigned Opcode = MCID.getOpcode();
343 const MCInstrDesc &MCID = MI->getDesc(); local
351 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
361 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
H A DThumb2ITBlockPass.cpp140 const MCInstrDesc &MCID = MI->getDesc(); local
142 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
H A DThumb1RegisterInfo.cpp241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
243 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)
291 const MCInstrDesc &MCID = TII.get(ExtraOpc); local
292 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
319 const MCInstrDesc &MCID = TII.get(ARM::tRSB);
320 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
H A DARMBaseRegisterInfo.cpp553 const MCInstrDesc &MCID = TII.get(ADDriOpc); local
556 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
558 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
/external/llvm/include/llvm/CodeGen/
H A DMachineInstr.h70 const MCInstrDesc *MCID; // Instruction descriptor. member in class:llvm::MachineInstr
112 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
257 const MCInstrDesc &getDesc() const { return *MCID; }
261 int getOpcode() const { return MCID->Opcode; }
329 return hasProperty(MCID::Variadic, Type);
335 return hasProperty(MCID::HasOptionalDef, Type);
342 return hasProperty(MCID::Pseudo, Type);
346 return hasProperty(MCID::Return, Type);
350 return hasProperty(MCID::Call, Type);
357 return hasProperty(MCID
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H A DMachineInstrBuilder.h225 const MCInstrDesc &MCID) {
226 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
234 const MCInstrDesc &MCID,
236 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
247 const MCInstrDesc &MCID,
250 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
258 const MCInstrDesc &MCID,
261 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
269 const MCInstrDesc &MCID,
273 return BuildMI(BB, MII, DL, MCID, DestRe
223 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID) argument
232 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
244 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
255 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
266 BuildMI(MachineBasicBlock &BB, MachineInstr *I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
284 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID) argument
294 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, DebugLoc DL, const MCInstrDesc &MCID) argument
304 BuildMI(MachineBasicBlock &BB, MachineInstr *I, DebugLoc DL, const MCInstrDesc &MCID) argument
321 BuildMI(MachineBasicBlock *BB, DebugLoc DL, const MCInstrDesc &MCID) argument
331 BuildMI(MachineBasicBlock *BB, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
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/external/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
129 if (MCID == NULL) {
133 unsigned idx = MCID->getSchedClass();
184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
185 assert(MCID && "The scheduler must filter non-machineinstrs");
186 if (DAG->TII->isZeroCost(MCID->Opcode))
193 unsigned idx = MCID->getSchedClass();
H A DTargetInstrInfo.cpp39 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, argument
42 if (OpNum >= MCID.getNumOperands())
45 short RegClass = MCID.OpInfo[OpNum].RegClass;
46 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
120 const MCInstrDesc &MCID = MI->getDesc(); local
121 bool HasDef = MCID.getNumDefs();
185 const MCInstrDesc &MCID = MI->getDesc(); local
186 if (!MCID.isCommutable())
190 SrcOpIdx1 = MCID.getNumDefs();
220 const MCInstrDesc &MCID local
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H A DMachineInstr.cpp521 if (MCID->ImplicitDefs)
522 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
524 if (MCID->ImplicitUses)
525 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
534 : MCID(&tid), Parent(0), Operands(0), NumOperands(0),
538 if (unsigned NumOps = MCID->getNumOperands() +
539 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
551 : MCID(&MI.getDesc()), Parent(0), Operands(0), NumOperands(0),
623 assert(MCID
1084 const MCInstrDesc &MCID = getDesc(); local
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H A DMachineVerifier.cpp760 const MCInstrDesc &MCID = MI->getDesc(); local
761 if (MI->getNumOperands() < MCID.getNumOperands()) {
763 *OS << MCID.getNumOperands() << " operands expected, but "
804 const MCInstrDesc &MCID = MI->getDesc(); local
806 // The first MCID.NumDefs operands must be explicit register defines
807 if (MONum < MCID.getNumDefs()) {
808 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
815 } else if (MONum < MCID.getNumOperands()) {
816 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
820 !(MI->isVariadic() && MONum == MCID
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H A DPeepholeOptimizer.cpp421 const MCInstrDesc &MCID = MI->getDesc(); local
422 if (MCID.getNumDefs() != 1)
441 const MCInstrDesc &MCID = MI->getDesc(); local
444 if (MCID.getNumDefs() != 1)
H A DRegAllocFast.cpp805 const MCInstrDesc &MCID = MI->getDesc(); local
924 MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1;
954 (hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) {
1010 SkippedInstrs.insert(&MCID);
/external/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
28 if (!MCID)
94 const MCInstrDesc &MCID = TII.get(Opcode); local
96 isLoad = MCID.mayLoad();
97 isStore = MCID.mayStore();
99 uint64_t TSFlags = MCID.TSFlags;
/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h152 const MCInstrDesc &MCID = MI->getDesc(); local
154 if (MCID.mayLoad())
156 if (MCID.mayStore())
/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp257 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local
258 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
259 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
264 if (MCID.isCommutable())
435 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local
436 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
437 unsigned NumRes = MCID.getNumDefs();
438 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
513 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); local
514 if (!MCID
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H A DInstrEmitter.cpp308 const MCInstrDesc &MCID = MIB->getDesc(); local
309 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
310 MCID.OpInfo[IIOpNum].isOptionalDef();
345 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
802 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
803 UsedRegs.append(MCID.getImplicitUses(),
804 MCID.getImplicitUses() + MCID.getNumImplicitUses());
H A DScheduleDAGSDNodes.cpp299 const MCInstrDesc &MCID = TII->get(Opc);
300 if (MCID.mayLoad())
434 const MCInstrDesc &MCID = TII->get(Opc);
435 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
436 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
441 if (MCID.isCommutable())
H A DScheduleDAGRRList.cpp1002 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local
1003 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
1004 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
1009 if (MCID.isCommutable())
1192 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local
1193 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
1194 unsigned NumRes = MCID.getNumDefs();
1195 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
1318 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); local
1319 if (!MCID
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/external/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp108 const MCInstrDesc &MCID = get(Opc); local
109 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);

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