Searched defs:MIB (Results 1 - 25 of 45) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
H A DPPCInstrBuilder.h33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, argument
36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrBuilder.h25 /// Add a BDX memory reference for frame object FI to MIB.
27 addFrameReference(const MachineInstrBuilder &MIB, int FI) { argument
28 MachineInstr *MI = MIB;
43 return MIB.addFrameIndex(FI).addImm(Offset).addReg(0).addMemOperand(MMO);
H A DSystemZFrameLowering.cpp105 // Add GPR64 to the save instruction being built by MIB, which is in basic
109 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB, argument
115 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
174 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG)); local
177 addSavedGPR(MBB, MIB, LowGPR, false);
178 addSavedGPR(MBB, MIB, HighGPR, false);
181 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
188 addSavedGPR(MBB, MIB, Reg, true);
194 addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
244 MachineInstrBuilder MIB local
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/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h136 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
327 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { argument
328 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
332 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { argument
333 return MIB.addReg(0);
337 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, argument
339 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
343 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { argument
344 return MIB.addReg(0);
H A DARMInstrInfo.cpp128 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL, variable
132 MIB.addImm(0);
133 AddDefaultPred(MIB); variable
139 MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
143 AddDefaultPred(MIB); variable
H A DThumb2InstrInfo.cpp157 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); local
158 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
159 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
160 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
161 AddDefaultPred(MIB);
198 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8)); local
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
201 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
202 AddDefaultPred(MIB);
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H A DThumb1FrameLowering.cpp400 MachineInstrBuilder MIB = local
403 AddDefaultPred(MIB);
404 MIB.copyImplicitOps(&*MBBI);
424 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); local
425 AddDefaultPred(MIB);
443 MIB.addReg(Reg, getKillRegState(isKill));
445 MIB.setMIFlags(MachineInstr::FrameSetup);
463 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)); local
464 AddDefaultPred(MIB);
474 (*MIB)
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H A DThumb1RegisterInfo.cpp128 MachineInstrBuilder MIB = local
131 MIB = AddDefaultT1CC(MIB);
133 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
135 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
136 AddDefaultPred(MIB);
240 const MachineInstrBuilder MIB =
243 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
259 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); local
261 MIB
267 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); local
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H A DThumb2ITBlockPass.cpp183 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT)) local
191 MachineBasicBlock::iterator InsertPos = MIB;
239 MIB.addImm(Mask);
H A DMLxExpansionPass.cpp293 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) local
297 MIB.addImm(LaneImm);
298 MIB.addImm(Pred).addReg(PredReg);
300 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
305 MIB.addReg(TmpReg, getKillRegState(true))
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
310 MIB.addImm(Pred).addReg(PredReg);
H A DARMBaseRegisterInfo.cpp598 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) local
602 AddDefaultCC(MIB);
/external/llvm/lib/CodeGen/
H A DMachineInstrBundle.cpp110 MachineInstrBuilder MIB = BuildMI(*MBB.getParent(), FirstMI->getDebugLoc(), local
112 Bundle.prepend(MIB);
191 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
200 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
H A DTargetLoweringBase.cpp941 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); local
945 MIB.addOperand(MI->getOperand(i));
947 MIB.addImm(StackMaps::DirectMemRefOp);
948 MIB.addOperand(MI->getOperand(OperIdx));
949 MIB.addImm(0);
952 MIB.addOperand(MI->getOperand(i));
955 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
956 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
966 MIB->addMemOperand(MF, MMO);
969 MBB->insert(MachineBasicBlock::iterator(MI), MIB); local
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp207 MachineInstrBuilder &MIB,
240 MIB.addReg(VRBase, RegState::Define);
253 MIB.addReg(VRBase, RegState::Define);
265 MIB.addReg(VRBase, RegState::Define);
307 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, argument
320 const MCInstrDesc &MCID = MIB->getDesc();
352 unsigned Idx = MIB->getNumOperands();
354 MIB->getOperand(Idx-1).isReg() &&
355 MIB->getOperand(Idx-1).isImplicit())
362 MIB
206 CreateVirtualRegisters(SDNode *Node, MachineInstrBuilder &MIB, const MCInstrDesc &II, bool IsClone, bool IsCloned, DenseMap<SDValue, unsigned> &VRBaseMap) argument
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/external/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp266 MachineInstrBuilder MIB = local
270 DEBUG(dbgs() << " adding copy: " << *MIB);
272 return MIB;
H A DAArch64BranchRelaxation.cpp430 MachineInstrBuilder MIB = BuildMI( local
435 MIB.addOperand(MI->getOperand(1));
437 invertBccCondition(MIB);
438 MIB.addMBB(NextBB);
H A DAArch64ConditionalCompares.cpp656 MachineInstrBuilder MIB = local
660 MIB.addImm(0); // cbz/cbnz Rn -> ccmp Rn, #0
662 MIB.addOperand(CmpMI->getOperand(FirstOp + 1)); // Register Rm / Immediate
663 MIB.addImm(NZCV).addImm(HeadCmpBBCC);
H A DAArch64LoadStoreOptimizer.cpp311 MachineInstrBuilder MIB = BuildMI(*I->getParent(), InsertionPoint, local
317 (void)MIB;
327 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
539 MachineInstrBuilder MIB = local
545 (void)MIB;
553 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
582 MachineInstrBuilder MIB = local
588 (void)MIB;
596 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
H A DAArch64FrameLowering.cpp678 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc)); local
680 MIB.addReg(AArch64::SP, RegState::Define);
682 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2))
748 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdrOpc)); local
750 MIB.addReg(AArch64::SP, RegState::Define);
752 MIB.addReg(Reg2, getDefRegState(true))
H A DAArch64InstrInfo.cpp263 const MachineInstrBuilder MIB = local
266 MIB.addImm(Cond[3].getImm());
267 MIB.addMBB(TBB);
1247 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE))
1252 return &*MIB;
1255 static const MachineInstrBuilder &AddSubReg(const MachineInstrBuilder &MIB,
1260 return MIB.addReg(Reg, State);
1263 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
1264 return MIB.addReg(Reg, State, SubIdx);
1293 const MachineInstrBuilder &MIB
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/external/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp182 MachineInstrBuilder MIB = local
185 MIB->copyImplicitOps(*MBB.getParent(), &*MBBI);
/external/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp103 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); local
107 MIB.addReg(Cond[i].getReg());
109 MIB.addImm(Cond[i].getImm());
113 MIB.addMBB(TBB);
287 MachineInstrBuilder MIB; local
288 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
291 MIB.addOperand(I->getOperand(J));
293 MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
294 return MIB;
H A DMipsLongBranch.cpp224 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); local
234 MIB.addReg(MO.getReg());
237 MIB.addMBB(MBBOpnd);
243 MIBundleBuilder(&*MIB).append((++II)->removeFromBundle());
H A DMips16InstrInfo.cpp87 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); local
90 MIB.addReg(DestReg, RegState::Define);
93 MIB.addReg(SrcReg, getKillRegState(KillSrc));
173 static void addSaveRestoreRegs(MachineInstrBuilder &MIB, argument
186 MIB.addReg(Reg, Flags);
205 MachineInstrBuilder MIB; local
207 MIB = BuildMI(MBB, I, DL, get(Opc));
209 addSaveRestoreRegs(MIB, CSI);
211 MIB.addReg(Mips::S2);
213 MIB
235 MachineInstrBuilder MIB; local
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/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h91 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { argument
94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
99 addOffset(const MachineInstrBuilder &MIB, int Offset) { argument
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
108 addRegOffset(const MachineInstrBuilder &MIB, argument
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
115 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, argument
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
123 addFullAddress(const MachineInstrBuilder &MIB, argument
128 MIB
149 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) argument
175 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, unsigned GlobalBaseReg, unsigned char OpFlags) argument
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