Searched refs:MBB (Results 76 - 100 of 306) sorted by relevance

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/external/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp57 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
88 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot);
92 bool tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
110 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { argument
115 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
123 Changed |= tryCombineRestoreWithPrevInst(MBB, MI);
130 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
139 MachineBasicBlock::iterator D = MBB.end();
142 D = findDelayInstr(MBB, M
169 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot) argument
466 tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) argument
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/external/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp108 MachineBasicBlock* MBB = MBBb; local
111 MachineBasicBlock::iterator MII = MBB->getFirstTerminator();
112 if (MII != MBB->end()) {
146 unsigned NumSuccs = MBB->succ_size();
147 MachineBasicBlock::succ_iterator SI = MBB->succ_begin();
153 if (MBB->isLayoutSuccessor(FirstSucc)) {
156 } else if (MBB->isLayoutSuccessor(SecondSucc)) {
192 MBB->removeSuccessor(JumpAroundTarget);
193 MBB->addSuccessor(UncondTarget);
/external/llvm/lib/Target/R600/
H A DR600InstrInfo.h40 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
46 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
64 void copyPhysReg(MachineBasicBlock &MBB,
68 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
163 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
166 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override;
168 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
175 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
178 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
221 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
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H A DAMDGPUInstrInfo.h45 MachineBasicBlock &MBB) const;
77 virtual void copyPhysReg(MachineBasicBlock &MBB,
84 void storeRegToStackSlot(MachineBasicBlock &MBB,
89 void loadRegFromStackSlot(MachineBasicBlock &MBB,
129 void insertNoop(MachineBasicBlock &MBB,
167 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
175 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
181 virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
H A DSIMachineFunctionInfo.cpp59 for (MachineBasicBlock &MBB : *MF) {
60 if (MBB.back().getOpcode() == AMDGPU::S_ENDPGM) {
61 MBB.back().addOperand(*MF, MachineOperand::CreateReg(VGPR, false, true));
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600InstrInfo.h43 virtual void copyPhysReg(MachineBasicBlock &MBB,
68 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
71 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
73 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
80 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
83 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
H A DAMDILFrameLowering.h42 virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
/external/llvm/include/llvm/CodeGen/
H A DLivePhysRegs.h114 /// \brief Adds all live-in registers of basic block @p MBB.
115 void addLiveIns(const MachineBasicBlock *MBB) { argument
116 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
117 LE = MBB->livein_end(); LI != LE; ++LI)
121 /// \brief Adds all live-out registers of basic block @p MBB.
122 void addLiveOuts(const MachineBasicBlock *MBB) { argument
123 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
124 SE = MBB->succ_end(); SI != SE; ++SI)
H A DMachineBlockFrequencyInfo.h1 //===- MachineBlockFrequencyInfo.h - MBB Frequency Analysis -*- C++ -*-----===//
51 BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const;
63 const MachineBasicBlock *MBB) const;
H A DMachineBranchProbabilityInfo.h60 uint32_t getSumForBlock(const MachineBasicBlock *MBB, uint32_t &Scale) const;
68 MachineBasicBlock *getHotSucc(MachineBasicBlock *MBB) const;
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600InstrInfo.h43 virtual void copyPhysReg(MachineBasicBlock &MBB,
68 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
71 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
73 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
80 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
83 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
H A DAMDILFrameLowering.h42 virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
/external/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp90 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, argument
94 const MachineFunction *MF = MBB.getParent();
149 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, argument
164 DebugLoc DL = MBB.findDebugLoc(MBBI);
172 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
177 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
189 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
192 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
207 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
209 if (MBBI == MBB
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/external/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp64 unsigned createDupLane(MachineBasicBlock &MBB,
70 unsigned createExtractSubreg(MachineBasicBlock &MBB,
76 unsigned createVExt(MachineBasicBlock &MBB,
81 unsigned createRegSequence(MachineBasicBlock &MBB,
86 unsigned createInsertSubreg(MachineBasicBlock &MBB,
91 unsigned createImplicitDef(MachineBasicBlock &MBB,
425 A15SDOptimizer::createDupLane(MachineBasicBlock &MBB, argument
431 AddDefaultPred(BuildMI(MBB,
444 A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB, argument
450 BuildMI(MBB,
461 createRegSequence(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned Reg1, unsigned Reg2) argument
480 createVExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned Ssub0, unsigned Ssub1) argument
496 createInsertSubreg(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned DReg, unsigned Lane, unsigned ToInsert) argument
513 createImplicitDef(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL) argument
531 MachineBasicBlock &MBB = *MI->getParent(); local
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H A DARMOptimizeBarriersPass.cpp59 for (auto &MBB : MF) {
63 for (auto &MI : MBB) {
H A DThumb2RegisterInfo.h31 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
/external/llvm/lib/CodeGen/AsmPrinter/
H A DDbgValueHistoryCalculator.cpp126 // \brief Returns the first instruction in @MBB which corresponds to
127 // the function epilogue, or nullptr if @MBB doesn't contain an epilogue.
128 static const MachineInstr *getFirstEpilogueInst(const MachineBasicBlock &MBB) { argument
129 auto LastMI = MBB.getLastNonDebugInstr();
130 if (LastMI == MBB.end() || !LastMI->isReturn())
136 for (MachineBasicBlock::const_reverse_iterator I(std::next(LastMI)); I != MBB.rend();
142 // If all instructions have the same debug location, assume whole MBB is
144 return MBB.begin();
152 for (const auto &MBB : *MF) {
153 auto FirstEpilogueInst = getFirstEpilogueInst(MBB);
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/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2568 // Create a new basic block after MBB.
2569 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) { argument
2570 MachineFunction &MF = *MBB->getParent();
2571 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
2572 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
2576 // Split MBB after MI and return the new block (the one that contains
2579 MachineBasicBlock *MBB) {
2580 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2581 NewMBB->splice(NewMBB->begin(), MBB,
2582 std::next(MachineBasicBlock::iterator(MI)), MBB
2578 splitBlockAfter(MachineInstr *MI, MachineBasicBlock *MBB) argument
2588 splitBlockBefore(MachineInstr *MI, MachineBasicBlock *MBB) argument
2661 emitCondStore(MachineInstr *MI, MachineBasicBlock *MBB, unsigned StoreOpcode, unsigned STOCOpcode, bool Invert) const argument
2728 emitAtomicLoadBinary(MachineInstr *MI, MachineBasicBlock *MBB, unsigned BinOpcode, unsigned BitSize, bool Invert) const argument
2852 emitAtomicLoadMinMax(MachineInstr *MI, MachineBasicBlock *MBB, unsigned CompareOpcode, unsigned KeepOldMask, unsigned BitSize) const argument
3083 emitExt128(MachineInstr *MI, MachineBasicBlock *MBB, bool ClearEven, unsigned SubReg) const argument
3115 emitMemMemWrapper(MachineInstr *MI, MachineBasicBlock *MBB, unsigned Opcode) const argument
3285 emitStringWrapper(MachineInstr *MI, MachineBasicBlock *MBB, unsigned Opcode) const argument
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H A DSystemZShortenInst.cpp33 bool processBlock(MachineBasicBlock &MBB);
100 // Process all instructions in MBB. Return true if something changed.
101 bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
107 for (auto SI = MBB.succ_begin(), SE = MBB.succ_end(); SI != SE; ++SI) {
118 for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
156 for (auto &MBB : F)
157 Changed |= processBlock(MBB);
/external/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp278 const MachineBasicBlock &MBB = *BI; local
279 if (MBB.empty() || !MBB.back().isReturn())
281 const MachineInstr &Ret = MBB.back();
496 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB local
497 MachineBasicBlock::iterator MBBI = MBB.begin();
521 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
529 MBBI = MBB.begin();
620 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
627 BuildMI(MBB, MBB
1359 spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
1426 restoreCRs(bool isPPC64, bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) argument
1463 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
1504 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
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H A DPPCRegisterInfo.cpp275 MachineBasicBlock &MBB = *MI.getParent(); local
277 MachineFunction &MF = *MBB.getParent();
308 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
312 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
316 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
333 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
338 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
344 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
348 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
358 BuildMI(MBB, I
395 MachineBasicBlock &MBB = *MI.getParent(); local
439 MachineBasicBlock &MBB = *MI.getParent(); local
512 MachineBasicBlock &MBB = *MI.getParent(); local
555 MachineBasicBlock &MBB = *MI.getParent(); local
602 MachineBasicBlock &MBB = *MI.getParent(); local
627 MachineBasicBlock &MBB = *MI.getParent(); local
705 MachineBasicBlock &MBB = *MI.getParent(); local
943 materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const argument
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H A DPPCFrameLowering.h37 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
49 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
55 MachineBasicBlock &MBB,
58 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
/external/llvm/lib/Target/Mips/
H A DMipsLongBranch.cpp78 void splitMBB(MachineBasicBlock *MBB);
81 void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL,
112 assert(false && "This instruction does not have an MBB operand.");
126 // Split MBB if it has two direct jumps/branches.
127 void MipsLongBranch::splitMBB(MachineBasicBlock *MBB) { argument
128 ReverseIter End = MBB->rend();
129 ReverseIter LastBr = getNonDebugInstr(MBB->rbegin(), End);
131 // Return if MBB has no branch instructions.
138 // MBB has only one branch instruction if FirstBr is not a branch
146 // Create a new MBB
175 MachineBasicBlock *MBB = MF->getBlockNumbered(I); local
217 replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL, MachineBasicBlock *MBBOpnd) argument
250 MachineBasicBlock *MBB = I.Br->getParent(), *TgtMBB = getTargetMBB(*I.Br); local
438 MachineBasicBlock &MBB = F.front(); local
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H A DMipsSERegisterInfo.cpp166 MachineBasicBlock &MBB = *MI.getParent(); local
171 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
175 MBB.getParent()->getTarget().getInstrInfo());
176 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset);
184 MachineBasicBlock &MBB = *MI.getParent(); local
190 MBB.getParent()->getTarget().getInstrInfo());
191 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
193 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
/external/llvm/lib/CodeGen/
H A DMachineCSE.cpp37 "Number of cross-MBB physreg referencing CS eliminated");
81 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
86 const MachineBasicBlock *MBB,
97 void EnterScope(MachineBasicBlock *MBB);
98 void ExitScope(MachineBasicBlock *MBB);
99 bool ProcessBlock(MachineBasicBlock *MBB);
116 MachineBasicBlock *MBB) {
210 const MachineBasicBlock *MBB,
225 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
249 if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB
115 PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB) argument
209 hasLivePhysRegDefUses(const MachineInstr *MI, const MachineBasicBlock *MBB, SmallSet<unsigned,8> &PhysRefs, SmallVectorImpl<unsigned> &PhysDefs, bool &PhysUseDef) const argument
268 const MachineBasicBlock *MBB = MI->getParent(); local
428 EnterScope(MachineBasicBlock *MBB) argument
434 ExitScope(MachineBasicBlock *MBB) argument
442 ProcessBlock(MachineBasicBlock *MBB) argument
652 MachineBasicBlock *MBB = Node->getBlock(); local
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