Searched refs:MRI (Results 201 - 225 of 247) sorted by relevance

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/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h156 const MachineRegisterInfo *MRI) const override;
/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp585 MRI.constrainRegClass(ResultReg, &AArch64::GPR32RegClass);
674 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
798 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
1043 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
1172 MRI.constrainRegClass(SrcReg, SrcVT == MVT::i64 ? &AArch64::GPR64RegClass
1601 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1693 MRI.constrainRegClass(Reg32, &AArch64::GPR32RegClass);
1716 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
1726 unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
1797 unsigned Src64 = MRI
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/external/llvm/lib/CodeGen/
H A DMachineBasicBlock.cpp361 MachineRegisterInfo &MRI = getParent()->getRegInfo(); local
369 if (!MRI.constrainRegClass(VirtReg, RC))
375 unsigned VirtReg = MRI.createVirtualRegister(RC);
880 MachineRegisterInfo *MRI = &getParent()->getRegInfo(); local
881 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
H A DScheduleDAGInstrs.cpp63 assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
383 if (MRI.hasOneDef(Reg))
777 VRegDefs.setUniverse(MRI.getNumVirtRegs());
778 VRegUses.setUniverse(MRI.getNumVirtRegs());
1149 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1184 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
H A DSplitKit.cpp134 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
135 for (MachineOperand &MO : MRI.use_nodbg_operands(CurLI->reg))
330 MRI(vrm.getMachineFunction().getRegInfo()),
972 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
973 RE = MRI.reg_end(); RI != RE;) {
1119 ConEQ.Distribute(&dups[0], MRI);
H A DCriticalAntiDepBreaker.cpp33 MRI(MF.getRegInfo()),
570 if (!MRI.isAllocatable(AntiDepReg))
H A DMachineModuleInfo.cpp254 const MCRegisterInfo &MRI,
256 : ImmutablePass(ID), Context(&MAI, &MRI, MOFI, nullptr, false) {
253 MachineModuleInfo(const MCAsmInfo &MAI, const MCRegisterInfo &MRI, const MCObjectFileInfo *MOFI) argument
H A DAggressiveAntiDepBreaker.cpp121 MRI(MF.getRegInfo()),
632 if (!MRI.isAllocatable(NewSuperReg)) continue;
815 if (!MRI.isAllocatable(AntiDepReg)) {
H A DLiveInterval.cpp901 MachineRegisterInfo &MRI) {
906 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LI.reg),
907 RE = MRI.reg_end(); RI != RE;) {
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1848 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1856 MachineInstr *Def = MRI->getVRegDef(VR);
1997 const MachineRegisterInfo *MRI = &MF.getRegInfo(); local
2025 MFI, MRI, TII))
6300 MachineRegisterInfo *MRI = &MF->getRegInfo(); local
6334 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6339 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6344 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6361 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6365 unsigned NewVReg2 = MRI
1847 MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument
6415 MachineRegisterInfo *MRI = &MF->getRegInfo(); local
6941 MachineRegisterInfo &MRI = MF->getRegInfo(); local
7202 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local
7423 MachineRegisterInfo &MRI = Fn->getRegInfo(); local
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H A DARMLoadStoreOptimizer.cpp1770 MachineRegisterInfo *MRI; member in struct:__anon25981::ARMPreAllocLoadStoreOpt
1800 MRI = &Fn.getRegInfo();
2051 MRI->constrainRegClass(EvenReg, TRC);
2052 MRI->constrainRegClass(OddReg, TRC);
2088 MRI->setRegAllocationHint(EvenReg, ARMRI::RegPairEven, OddReg);
2089 MRI->setRegAllocationHint(OddReg, ARMRI::RegPairOdd, EvenReg);
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp134 const MCRegisterInfo *MRI; member in class:__anon25986::ARMAsmParser
339 MRI = getContext().getRegisterInfo();
3306 EReg = MRI->getEncodingValue(Reg);
3321 EReg = MRI->getEncodingValue(Reg);
3346 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3352 EReg = MRI->getEncodingValue(Reg);
3374 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3380 if (MRI
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/external/llvm/lib/MC/
H A DMCDwarf.cpp1339 const MCRegisterInfo *MRI = context.getRegisterInfo(); local
1394 assert(MRI->getRARegister() <= 255 &&
1396 streamer.EmitIntValue(MRI->getDwarfRegNum(MRI->getRARegister(), true), 1);
1399 MRI->getDwarfRegNum(MRI->getRARegister(), true));
H A DMCContext.cpp35 : SrcMgr(mgr), MAI(mai), MRI(mri), MOFI(mofi), Allocator(),
/external/llvm/lib/MC/MCParser/
H A DCOFFAsmParser.cpp733 const MCRegisterInfo *MRI = getContext().getRegisterInfo(); local
753 int SEHRegNo = MRI->getSEHRegNum(LLVMRegNo);
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp37 const MCRegisterInfo &MRI,
44 const MCRegisterInfo &MRI,
36 createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
43 createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp283 const MachineRegisterInfo &MRI = MF->getRegInfo(); local
287 if (MRI.use_empty(reg))
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.h27 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.h253 const MachineRegisterInfo *MRI; member in class:llvm::NVPTXAsmPrinter
/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp956 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local
957 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
981 MachineRegisterInfo &MRI = MF.getRegInfo();
982 MRI.constrainRegClass(BaseReg,
/external/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp189 MachineRegisterInfo &MRI = MF->getRegInfo(); local
202 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()))
244 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
279 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
280 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
380 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
381 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
633 MachineRegisterInfo &MRI = MF.getRegInfo(); local
634 MRI.addLiveIn(Reg);
654 MachineRegisterInfo &MRI local
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/external/llvm/lib/Target/X86/
H A DX86RegisterInfo.cpp427 const MachineRegisterInfo *MRI = &MF.getRegInfo(); local
431 if (!MRI->canReserveReg(FramePtr))
437 return MRI->canReserveReg(BasePtr);
H A DX86FrameLowering.cpp316 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
329 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
344 const MachineRegisterInfo &MRI = MF.getRegInfo();
347 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
/external/llvm/include/llvm/CodeGen/
H A DLiveInterval.h677 void Distribute(LiveInterval *LIV[], MachineRegisterInfo &MRI);
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp154 const MCRegisterInfo &MRI,
153 createPPCMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument

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