/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.h | 156 const MachineRegisterInfo *MRI) const override;
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 585 MRI.constrainRegClass(ResultReg, &AArch64::GPR32RegClass); 674 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass); 798 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass); 1043 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass); 1172 MRI.constrainRegClass(SrcReg, SrcVT == MVT::i64 ? &AArch64::GPR64RegClass 1601 if (!MRI.getRegClass(SrcReg)->contains(DestReg)) 1693 MRI.constrainRegClass(Reg32, &AArch64::GPR32RegClass); 1716 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass); 1726 unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); 1797 unsigned Src64 = MRI [all...] |
/external/llvm/lib/CodeGen/ |
H A D | MachineBasicBlock.cpp | 361 MachineRegisterInfo &MRI = getParent()->getRegInfo(); local 369 if (!MRI.constrainRegClass(VirtReg, RC)) 375 unsigned VirtReg = MRI.createVirtualRegister(RC); 880 MachineRegisterInfo *MRI = &getParent()->getRegInfo(); local 881 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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H A D | ScheduleDAGInstrs.cpp | 63 assert(!(IsPostRA && MRI.getNumVirtRegs()) && 383 if (MRI.hasOneDef(Reg)) 777 VRegDefs.setUniverse(MRI.getNumVirtRegs()); 778 VRegUses.setUniverse(MRI.getNumVirtRegs()); 1149 if ((Reg == 0) || MRI.isReserved(Reg)) continue; 1184 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
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H A D | SplitKit.cpp | 134 const MachineRegisterInfo &MRI = MF.getRegInfo(); local 135 for (MachineOperand &MO : MRI.use_nodbg_operands(CurLI->reg)) 330 MRI(vrm.getMachineFunction().getRegInfo()), 972 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()), 973 RE = MRI.reg_end(); RI != RE;) { 1119 ConEQ.Distribute(&dups[0], MRI);
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H A D | CriticalAntiDepBreaker.cpp | 33 MRI(MF.getRegInfo()), 570 if (!MRI.isAllocatable(AntiDepReg))
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H A D | MachineModuleInfo.cpp | 254 const MCRegisterInfo &MRI, 256 : ImmutablePass(ID), Context(&MAI, &MRI, MOFI, nullptr, false) { 253 MachineModuleInfo(const MCAsmInfo &MAI, const MCRegisterInfo &MRI, const MCObjectFileInfo *MOFI) argument
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H A D | AggressiveAntiDepBreaker.cpp | 121 MRI(MF.getRegInfo()), 632 if (!MRI.isAllocatable(NewSuperReg)) continue; 815 if (!MRI.isAllocatable(AntiDepReg)) {
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H A D | LiveInterval.cpp | 901 MachineRegisterInfo &MRI) { 906 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LI.reg), 907 RE = MRI.reg_end(); RI != RE;) {
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 1848 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 1856 MachineInstr *Def = MRI->getVRegDef(VR); 1997 const MachineRegisterInfo *MRI = &MF.getRegInfo(); local 2025 MFI, MRI, TII)) 6300 MachineRegisterInfo *MRI = &MF->getRegInfo(); local 6334 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 6339 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 6344 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 6361 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 6365 unsigned NewVReg2 = MRI 1847 MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument 6415 MachineRegisterInfo *MRI = &MF->getRegInfo(); local 6941 MachineRegisterInfo &MRI = MF->getRegInfo(); local 7202 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local 7423 MachineRegisterInfo &MRI = Fn->getRegInfo(); local [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 1770 MachineRegisterInfo *MRI; member in struct:__anon25981::ARMPreAllocLoadStoreOpt 1800 MRI = &Fn.getRegInfo(); 2051 MRI->constrainRegClass(EvenReg, TRC); 2052 MRI->constrainRegClass(OddReg, TRC); 2088 MRI->setRegAllocationHint(EvenReg, ARMRI::RegPairEven, OddReg); 2089 MRI->setRegAllocationHint(OddReg, ARMRI::RegPairOdd, EvenReg);
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 134 const MCRegisterInfo *MRI; member in class:__anon25986::ARMAsmParser 339 MRI = getContext().getRegisterInfo(); 3306 EReg = MRI->getEncodingValue(Reg); 3321 EReg = MRI->getEncodingValue(Reg); 3346 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) 3352 EReg = MRI->getEncodingValue(Reg); 3374 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { 3380 if (MRI [all...] |
/external/llvm/lib/MC/ |
H A D | MCDwarf.cpp | 1339 const MCRegisterInfo *MRI = context.getRegisterInfo(); local 1394 assert(MRI->getRARegister() <= 255 && 1396 streamer.EmitIntValue(MRI->getDwarfRegNum(MRI->getRARegister(), true), 1); 1399 MRI->getDwarfRegNum(MRI->getRARegister(), true));
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H A D | MCContext.cpp | 35 : SrcMgr(mgr), MAI(mai), MRI(mri), MOFI(mofi), Allocator(),
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/external/llvm/lib/MC/MCParser/ |
H A D | COFFAsmParser.cpp | 733 const MCRegisterInfo *MRI = getContext().getRegisterInfo(); local 753 int SEHRegNo = MRI->getSEHRegNum(LLVMRegNo);
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 37 const MCRegisterInfo &MRI, 44 const MCRegisterInfo &MRI, 36 createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument 43 createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcAsmPrinter.cpp | 283 const MachineRegisterInfo &MRI = MF->getRegInfo(); local 287 if (MRI.use_empty(reg))
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/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.h | 27 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.h | 253 const MachineRegisterInfo *MRI; member in class:llvm::NVPTXAsmPrinter
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 956 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local 957 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 981 MachineRegisterInfo &MRI = MF.getRegInfo(); 982 MRI.constrainRegClass(BaseReg,
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/external/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 189 MachineRegisterInfo &MRI = MF->getRegInfo(); local 202 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg())) 244 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister); 279 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 280 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 380 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 381 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 633 MachineRegisterInfo &MRI = MF.getRegInfo(); local 634 MRI.addLiveIn(Reg); 654 MachineRegisterInfo &MRI local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 427 const MachineRegisterInfo *MRI = &MF.getRegInfo(); local 431 if (!MRI->canReserveReg(FramePtr)) 437 return MRI->canReserveReg(BasePtr);
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H A D | X86FrameLowering.cpp | 316 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); 329 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 344 const MachineRegisterInfo &MRI = MF.getRegInfo(); 347 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
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/external/llvm/include/llvm/CodeGen/ |
H A D | LiveInterval.h | 677 void Distribute(LiveInterval *LIV[], MachineRegisterInfo &MRI);
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 154 const MCRegisterInfo &MRI, 153 createPPCMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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