| /external/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 48 const ARMSubtarget *STI; member in class:__anon25968::ARMExpandPseudo
662 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO);
665 if (!STI->hasV6T2Ops() &&
668 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
1348 STI = &TM.getSubtarget<ARMSubtarget>();
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| H A D | ARMConstantIslandPass.cpp | 261 const ARMSubtarget *STI; member in class:__anon25967::ARMConstantIslands
387 STI = &MF->getTarget().getSubtarget<ARMSubtarget>();
471 if (isThumb2 && !STI->prefers32BitThumb())
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| H A D | ARMAsmPrinter.cpp | 401 static bool isThumb(const MCSubtargetInfo& STI) { argument
402 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
|
| H A D | ARMBaseInstrInfo.cpp | 93 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) argument
95 Subtarget(STI) {
107 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, argument
111 &static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
114 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
|
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 215 MCSubtargetInfo &STI; member in class:__anon26071::PPCAsmParser
268 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
270 Triple TheTriple(STI.getTargetTriple());
275 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
934 Out.EmitInstruction(Inst, STI);
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMELFStreamer.cpp | 484 const MCSubtargetInfo &STI) override {
490 MCELFStreamer::EmitInstruction(Inst, STI);
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsConstantIslandPass.cpp | 347 const MipsSubtarget *STI; member in class:__anon26048::MipsConstantIslands
371 STI(&TM.getSubtarget<MipsSubtarget>()), MF(nullptr), MCP(nullptr),
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 43 MCSubtargetInfo &STI; member in class:__anon25951::AArch64AsmParser
119 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
125 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
2652 STI.getFeatureBits(), getContext()));
3821 Out.EmitInstruction(Inst, STI);
3981 getParser().getStreamer().EmitInstruction(Inst, STI);
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 131 MCSubtargetInfo &STI; member in class:__anon25986::ARMAsmParser
242 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
245 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
248 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
251 return STI.getFeatureBits() & ARM::HasV4TOps;
254 return STI.getFeatureBits() & ARM::HasV6Ops;
257 return STI.getFeatureBits() & ARM::HasV6MOps;
260 return STI.getFeatureBits() & ARM::HasV7Ops;
263 return STI.getFeatureBits() & ARM::HasV8Ops;
266 return !(STI
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 101 X86InstrInfo::X86InstrInfo(X86Subtarget &STI) argument
103 (STI.is64Bit() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
104 (STI.is64Bit() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
105 Subtarget(STI), RI(STI) {
3182 const X86Subtarget &STI,
3184 if (STI.hasAVX512()) {
3196 bool HasAVX = STI.hasAVX();
3202 if (STI.is64Bit())
3269 const X86Subtarget &STI) {
3179 getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI, bool load) argument
3266 getStoreRegOpcode(unsigned SrcReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI) argument
3274 getLoadRegOpcode(unsigned DestReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI) argument
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 31 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI) argument
33 RI(this, &STI), Subtarget(STI) {}
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| H A D | ARMInstPrinter.cpp | 64 const MCSubtargetInfo &STI) :
67 setAvailableFeatures(STI.getFeatureBits());
61 ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
|
| /external/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 674 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, argument
|
| /external/llvm/lib/MC/ |
| H A D | MCStreamer.cpp | 650 const MCSubtargetInfo &STI) {
649 EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) argument
|
| /external/chromium_org/third_party/mesa/src/src/mesa/x86/ |
| H A D | assyntax.h | 663 #define STI CHOICE(sti, sti, sti) macro
1384 #define STI sti macro
|
| /external/mesa3d/src/mesa/x86/ |
| H A D | assyntax.h | 663 #define STI CHOICE(sti, sti, sti) macro
1384 #define STI sti macro
|