/external/chromium_org/third_party/mesa/src/src/mesa/tnl_dd/ |
H A D | t_dd_tritmp.h | 296 TRI( v[0], v[1], v[2] ); 299 TRI( v[0], v[1], v[2] );
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineScheduler.h | 46 // DAG->addMutation(new CustomDependencies(DAG->TII, DAG->TRI)); 828 const TargetRegisterInfo *TRI; member in class:llvm::GenericSchedulerBase 833 Context(C), SchedModel(nullptr), TRI(nullptr) {}
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H A D | CallingConvLower.h | 178 const TargetRegisterInfo &TRI; member in class:llvm::CCState
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.cpp | 414 const TargetRegisterInfo *TRI) const { 453 const TargetRegisterInfo *TRI) const {
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16InstrInfo.cpp | 99 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, 116 const TargetRegisterInfo *TRI, int64_t Offset) const { 97 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument 114 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
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H A D | MipsSEFrameLowering.cpp | 452 const TargetRegisterInfo *TRI) const { 471 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 473 CSI[i].getFrameIdx(), RC, TRI);
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/external/mesa3d/src/mesa/tnl_dd/ |
H A D | t_dd_tritmp.h | 296 TRI( v[0], v[1], v[2] ); 299 TRI( v[0], v[1], v[2] );
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 69 const HexagonRegisterInfo *TRI; member in struct:__anon26012::HexagonHardwareLoops 269 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : nullptr; local 270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); } 306 TRI = static_cast<const HexagonRegisterInfo*>(TM->getRegisterInfo());
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H A D | HexagonVLIWPacketizer.cpp | 394 const TargetRegisterInfo *TRI) { 395 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) { 397 if (MI->modifiesRegister(CalleeSavedReg, TRI)) 393 DoesModifyCalleeSavedReg(MachineInstr *MI, const TargetRegisterInfo *TRI) argument
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.cpp | 444 const TargetRegisterInfo *TRI) { 468 if (MI->modifiesRegister(SystemZ::CC, TRI)) 594 const TargetRegisterInfo *TRI) const { 610 const TargetRegisterInfo *TRI) const { 442 removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI) argument
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDILCFGStructurizer.cpp | 406 const AMDGPURegisterInfo *TRI; member in class:llvmCFGStruct::CFGStructurizer 426 TRI = tri; 515 TRI = tri; 1343 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 1450 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 1484 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 1905 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 2181 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 2665 const AMDGPURegisterInfo *TRI; member in class:llvm::AMDGPUCFGStructurizer 2681 TRI(static_cas [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.cpp | 112 const TargetRegisterInfo *TRI, 129 TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo)); 477 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); 111 CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) argument
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H A D | FastISel.cpp | 1221 TRI(*TM.getRegisterInfo()), 1330 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF); 1432 RC = TII.getRegClass(II, II.getNumDefs(), &TRI, *FuncInfo.MF); 1591 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelDAGToDAG.cpp | 232 const AMDGPURegisterInfo *TRI = local 315 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32); 327 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
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H A D | AMDILCFGStructurizer.cpp | 138 MachineFunctionPass(ID), TII(nullptr), TRI(nullptr) { 164 TRI = &TII->getRegisterInfo(); 185 const AMDGPURegisterInfo *TRI; member in class:__anon26106::AMDGPUCFGStructurizer 1337 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 1721 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILCFGStructurizer.cpp | 406 const AMDGPURegisterInfo *TRI; member in class:llvmCFGStruct::CFGStructurizer 426 TRI = tri; 515 TRI = tri; 1343 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 1450 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 1484 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 1905 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 2181 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32); 2665 const AMDGPURegisterInfo *TRI; member in class:llvm::AMDGPUCFGStructurizer 2681 TRI(static_cas [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.cpp | 831 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local 832 if (TRI->isVirtualRegister(RegNo)) { 1976 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local 1977 //unsigned numRegClasses = TRI->getNumRegClasses(); 2000 unsigned int vr = TRI->index2VirtReg(i); 2019 for (unsigned i=0; i< TRI->getNumRegClasses(); i++) { 2020 const TargetRegisterClass *RC = TRI->getRegClass(i);
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/external/llvm/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 365 const TargetRegisterInfo &TRI, 364 EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII) argument
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H A D | TargetLoweringBase.cpp | 981 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); local 987 BitVector SuperRegRC(TRI->getNumRegClasses()); 988 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 994 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 1811 const TargetRegisterInfo &TRI) const { 1825 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 3285 const TargetRegisterInfo *TRI) const { 3324 const TargetRegisterInfo *TRI) const { 3674 const TargetRegisterInfo *TRI = &getRegisterInfo(); local 3696 if (Instr->modifiesRegister(X86::EFLAGS, TRI) || 3697 Instr->readsRegister(X86::EFLAGS, TRI)) { 3704 Instr->registerDefIsDead(X86::EFLAGS, TRI)) { 3730 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI); 3731 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI); [all...] |
/external/eigen/blas/testing/ |
H A D | cblat2.f | 2713 LOGICAL GEN, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:CMAKE 2722 TRI = TYPE( 1: 1 ).EQ.'T' 2723 UPPER = ( SYM.OR.TRI ).AND.UPLO.EQ.'U' 2724 LOWER = ( SYM.OR.TRI ).AND.UPLO.EQ.'L' 2725 UNIT = TRI.AND.DIAG.EQ.'U' 2742 ELSE IF( TRI )THEN 2750 IF( TRI )
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H A D | cblat3.f | 2907 LOGICAL GEN, HER, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:CMAKE 2917 TRI = TYPE.EQ.'TR' 2918 UPPER = ( HER.OR.SYM.OR.TRI ).AND.UPLO.EQ.'U' 2919 LOWER = ( HER.OR.SYM.OR.TRI ).AND.UPLO.EQ.'L' 2920 UNIT = TRI.AND.DIAG.EQ.'U' 2937 ELSE IF( TRI )THEN 2945 IF( TRI )
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H A D | dblat2.f | 2643 LOGICAL GEN, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:DMAKE 2652 TRI = TYPE( 1: 1 ).EQ.'T' 2653 UPPER = ( SYM.OR.TRI ).AND.UPLO.EQ.'U' 2654 LOWER = ( SYM.OR.TRI ).AND.UPLO.EQ.'L' 2655 UNIT = TRI.AND.DIAG.EQ.'U' 2672 ELSE IF( TRI )THEN 2678 IF( TRI )
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H A D | dblat3.f | 2376 LOGICAL GEN, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:DMAKE 2383 TRI = TYPE.EQ.'TR' 2384 UPPER = ( SYM.OR.TRI ).AND.UPLO.EQ.'U' 2385 LOWER = ( SYM.OR.TRI ).AND.UPLO.EQ.'L' 2386 UNIT = TRI.AND.DIAG.EQ.'U' 2401 ELSE IF( TRI )THEN 2407 IF( TRI )
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H A D | sblat2.f | 2643 LOGICAL GEN, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:SMAKE 2652 TRI = TYPE( 1: 1 ).EQ.'T' 2653 UPPER = ( SYM.OR.TRI ).AND.UPLO.EQ.'U' 2654 LOWER = ( SYM.OR.TRI ).AND.UPLO.EQ.'L' 2655 UNIT = TRI.AND.DIAG.EQ.'U' 2672 ELSE IF( TRI )THEN 2678 IF( TRI )
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