Searched refs:TRI (Results 176 - 200 of 233) sorted by relevance

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/external/chromium_org/third_party/mesa/src/src/mesa/tnl_dd/
H A Dt_dd_tritmp.h296 TRI( v[0], v[1], v[2] );
299 TRI( v[0], v[1], v[2] );
/external/llvm/include/llvm/CodeGen/
H A DMachineScheduler.h46 // DAG->addMutation(new CustomDependencies(DAG->TII, DAG->TRI));
828 const TargetRegisterInfo *TRI; member in class:llvm::GenericSchedulerBase
833 Context(C), SchedModel(nullptr), TRI(nullptr) {}
H A DCallingConvLower.h178 const TargetRegisterInfo &TRI; member in class:llvm::CCState
/external/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.cpp414 const TargetRegisterInfo *TRI) const {
453 const TargetRegisterInfo *TRI) const {
/external/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp99 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
116 const TargetRegisterInfo *TRI, int64_t Offset) const {
97 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
114 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
H A DMipsSEFrameLowering.cpp452 const TargetRegisterInfo *TRI) const {
471 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
473 CSI[i].getFrameIdx(), RC, TRI);
/external/mesa3d/src/mesa/tnl_dd/
H A Dt_dd_tritmp.h296 TRI( v[0], v[1], v[2] );
299 TRI( v[0], v[1], v[2] );
/external/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp69 const HexagonRegisterInfo *TRI; member in struct:__anon26012::HexagonHardwareLoops
269 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : nullptr; local
270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
306 TRI = static_cast<const HexagonRegisterInfo*>(TM->getRegisterInfo());
H A DHexagonVLIWPacketizer.cpp394 const TargetRegisterInfo *TRI) {
395 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
397 if (MI->modifiesRegister(CalleeSavedReg, TRI))
393 DoesModifyCalleeSavedReg(MachineInstr *MI, const TargetRegisterInfo *TRI) argument
/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp444 const TargetRegisterInfo *TRI) {
468 if (MI->modifiesRegister(SystemZ::CC, TRI))
594 const TargetRegisterInfo *TRI) const {
610 const TargetRegisterInfo *TRI) const {
442 removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI) argument
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDILCFGStructurizer.cpp406 const AMDGPURegisterInfo *TRI; member in class:llvmCFGStruct::CFGStructurizer
426 TRI = tri;
515 TRI = tri;
1343 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
1450 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
1484 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
1905 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
2181 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
2665 const AMDGPURegisterInfo *TRI; member in class:llvm::AMDGPUCFGStructurizer
2681 TRI(static_cas
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp112 const TargetRegisterInfo *TRI,
129 TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo));
477 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
111 CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) argument
H A DFastISel.cpp1221 TRI(*TM.getRegisterInfo()),
1330 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
1432 RC = TII.getRegClass(II, II.getNumDefs(), &TRI, *FuncInfo.MF);
1591 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
/external/llvm/lib/Target/R600/
H A DAMDGPUISelDAGToDAG.cpp232 const AMDGPURegisterInfo *TRI = local
315 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
327 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
H A DAMDILCFGStructurizer.cpp138 MachineFunctionPass(ID), TII(nullptr), TRI(nullptr) {
164 TRI = &TII->getRegisterInfo();
185 const AMDGPURegisterInfo *TRI; member in class:__anon26106::AMDGPUCFGStructurizer
1337 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
1721 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILCFGStructurizer.cpp406 const AMDGPURegisterInfo *TRI; member in class:llvmCFGStruct::CFGStructurizer
426 TRI = tri;
515 TRI = tri;
1343 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
1450 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
1484 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
1905 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
2181 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
2665 const AMDGPURegisterInfo *TRI; member in class:llvm::AMDGPUCFGStructurizer
2681 TRI(static_cas
[all...]
/external/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp831 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local
832 if (TRI->isVirtualRegister(RegNo)) {
1976 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local
1977 //unsigned numRegClasses = TRI->getNumRegClasses();
2000 unsigned int vr = TRI->index2VirtReg(i);
2019 for (unsigned i=0; i< TRI->getNumRegClasses(); i++) {
2020 const TargetRegisterClass *RC = TRI->getRegClass(i);
/external/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp365 const TargetRegisterInfo &TRI,
364 EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII) argument
H A DTargetLoweringBase.cpp981 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); local
987 BitVector SuperRegRC(TRI->getNumRegClasses());
988 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
994 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1811 const TargetRegisterInfo &TRI) const {
1825 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
3285 const TargetRegisterInfo *TRI) const {
3324 const TargetRegisterInfo *TRI) const {
3674 const TargetRegisterInfo *TRI = &getRegisterInfo(); local
3696 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3697 Instr->readsRegister(X86::EFLAGS, TRI)) {
3704 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3730 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3731 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
[all...]
/external/eigen/blas/testing/
H A Dcblat2.f2713 LOGICAL GEN, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:CMAKE
2722 TRI = TYPE( 1: 1 ).EQ.'T'
2723 UPPER = ( SYM.OR.TRI ).AND.UPLO.EQ.'U'
2724 LOWER = ( SYM.OR.TRI ).AND.UPLO.EQ.'L'
2725 UNIT = TRI.AND.DIAG.EQ.'U'
2742 ELSE IF( TRI )THEN
2750 IF( TRI )
H A Dcblat3.f2907 LOGICAL GEN, HER, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:CMAKE
2917 TRI = TYPE.EQ.'TR'
2918 UPPER = ( HER.OR.SYM.OR.TRI ).AND.UPLO.EQ.'U'
2919 LOWER = ( HER.OR.SYM.OR.TRI ).AND.UPLO.EQ.'L'
2920 UNIT = TRI.AND.DIAG.EQ.'U'
2937 ELSE IF( TRI )THEN
2945 IF( TRI )
H A Ddblat2.f2643 LOGICAL GEN, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:DMAKE
2652 TRI = TYPE( 1: 1 ).EQ.'T'
2653 UPPER = ( SYM.OR.TRI ).AND.UPLO.EQ.'U'
2654 LOWER = ( SYM.OR.TRI ).AND.UPLO.EQ.'L'
2655 UNIT = TRI.AND.DIAG.EQ.'U'
2672 ELSE IF( TRI )THEN
2678 IF( TRI )
H A Ddblat3.f2376 LOGICAL GEN, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:DMAKE
2383 TRI = TYPE.EQ.'TR'
2384 UPPER = ( SYM.OR.TRI ).AND.UPLO.EQ.'U'
2385 LOWER = ( SYM.OR.TRI ).AND.UPLO.EQ.'L'
2386 UNIT = TRI.AND.DIAG.EQ.'U'
2401 ELSE IF( TRI )THEN
2407 IF( TRI )
H A Dsblat2.f2643 LOGICAL GEN, LOWER, SYM, TRI, UNIT, UPPER local in subroutine:SMAKE
2652 TRI = TYPE( 1: 1 ).EQ.'T'
2653 UPPER = ( SYM.OR.TRI ).AND.UPLO.EQ.'U'
2654 LOWER = ( SYM.OR.TRI ).AND.UPLO.EQ.'L'
2655 UNIT = TRI.AND.DIAG.EQ.'U'
2672 ELSE IF( TRI )THEN
2678 IF( TRI )

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