Searched refs:TRI (Results 76 - 100 of 233) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
H A DVirtRegMap.h43 const TargetRegisterInfo *TRI; member in class:llvm::VirtRegMap
86 const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
H A DLiveRegMatrix.h40 const TargetRegisterInfo *TRI; member in class:llvm::LiveRegMatrix
H A DRegisterClassInfo.h52 const TargetRegisterInfo *TRI; member in class:llvm::RegisterClassInfo
117 /// This is the smallest value returned by TRI->getCostPerUse(Reg) for all
126 /// same cost according to TRI->getCostPerUse().
H A DStackMaps.h168 const TargetRegisterInfo *TRI) const;
194 void emitCallsiteEntries(MCStreamer &OS, const TargetRegisterInfo *TRI);
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h64 const TargetRegisterInfo *TRI,
221 const TargetRegisterInfo &TRI) const;
530 const TargetRegisterInfo *TRI) const {
543 const TargetRegisterInfo *TRI) const {
656 const TargetRegisterInfo *TRI) const {
982 const TargetRegisterInfo *TRI) const {
1002 const TargetRegisterInfo *TRI) const {
1026 const TargetRegisterInfo *TRI) const {}
H A DTargetRegisterInfo.h431 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
845 const TargetRegisterInfo *TRI,
847 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
883 /// Prints virtual and physical registers with or without a TRI instance.
888 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
890 /// %physreg17 - a physical register when no TRI instance given.
892 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
895 const TargetRegisterInfo *TRI; member in class:llvm::TargetRegisterInfo::PrintReg
901 : TRI(tri), Reg(reg), SubIdx(subidx) {}
917 /// Usage: OS << PrintRegUnit(Unit, TRI) << '\
921 const TargetRegisterInfo *TRI; member in class:llvm::TargetRegisterInfo::PrintRegUnit
[all...]
/external/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp54 const TargetRegisterInfo *TRI) const {
82 const TargetRegisterInfo *TRI) const {
H A DThumb2InstrInfo.cpp129 const TargetRegisterInfo *TRI) const {
158 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
159 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
165 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
172 const TargetRegisterInfo *TRI) const {
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
209 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
/external/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp109 const TargetRegisterInfo *TRI,
158 if (localBegin->modifiesRegister(Reg, TRI) ||
159 localBegin->readsRegister(Reg, TRI))
215 const TargetRegisterInfo *TRI,
267 if (localII->modifiesRegister(pReg, TRI) ||
268 localII->readsRegister(pReg, TRI))
278 if (localII->modifiesRegister(cmpReg1, TRI) ||
279 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
108 canBeFeederToNewValueJump(const HexagonInstrInfo *QII, const TargetRegisterInfo *TRI, MachineBasicBlock::iterator II, MachineBasicBlock::iterator end, MachineBasicBlock::iterator skip, MachineFunction &MF) argument
214 canCompareBeNewValueJump(const HexagonInstrInfo *QII, const TargetRegisterInfo *TRI, MachineBasicBlock::iterator II, unsigned pReg, bool secondReg, bool optLocation, MachineBasicBlock::iterator end, MachineFunction &MF) argument
/external/llvm/lib/Target/Mips/
H A DMips16InstrInfo.h55 const TargetRegisterInfo *TRI,
62 const TargetRegisterInfo *TRI,
/external/llvm/lib/CodeGen/
H A DMachineInstr.cpp69 const TargetRegisterInfo &TRI) {
72 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
78 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { argument
81 Reg = TRI.getSubReg(Reg, getSubReg());
268 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : nullptr; local
272 OS << PrintReg(getReg(), TRI, getSubReg()); local
970 const TargetRegisterInfo *TRI) const {
977 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
995 return TRI->getRegClass(RCID);
999 return TRI
68 substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &TRI) argument
1004 getRegClassConstraintEffectForVReg( unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle) const argument
1828 setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs, const TargetRegisterInfo &TRI) argument
[all...]
H A DLiveIntervalAnalysis.cpp114 TRI = TM->getRegisterInfo();
132 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
146 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
246 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
247 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
256 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
257 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
272 RegUnitRanges.resize(TRI->getNumRegUnits());
292 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
301 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VN
727 const TargetRegisterInfo& TRI; member in class:LiveIntervals::HMEditor
734 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI, const TargetRegisterInfo& TRI, SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags) argument
[all...]
H A DCriticalAntiDepBreaker.h38 const TargetRegisterInfo *TRI; member in class:llvm::CriticalAntiDepBreaker
H A DEarlyIfConversion.cpp83 const TargetRegisterInfo *TRI; member in class:__anon25739::SSAIfConv
157 TRI = MF.getTarget().getRegisterInfo();
160 LiveRegUnits.setUniverse(TRI->getNumRegUnits());
162 ClobberedRegUnits.resize(TRI->getNumRegUnits());
240 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
296 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
304 for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
320 dbgs() << ' ' << PrintRegUnit(*i, TRI);
582 const TargetRegisterInfo *TRI; member in class:__anon25740::EarlyIfConverter
786 TRI
[all...]
H A DExecutionDepsFix.cpp134 const TargetRegisterInfo *TRI; member in class:__anon25744::ExeDepsFix
203 /// Translate TRI register number to an index into our smaller tables of
500 unsigned Pref = TII->getUndefRegClearance(MI, OpNum, TRI);
521 DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
526 unsigned Pref = TII->getPartialRegUpdateClearance(MI, i, TRI);
528 TII->breakPartialRegDependency(MI, i, TRI);
551 LiveRegSet.init(TRI);
564 TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);
717 TRI = MF->getTarget().getRegisterInfo();
739 AliasMap.resize(TRI
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H A DMachineInstrBundle.cpp108 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local
174 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
282 const TargetRegisterInfo *TRI) {
301 bool IsRegOrSuperReg = MOReg == Reg || TRI->isSubRegister(MOReg, Reg);
302 bool IsRegOrOverlapping = MOReg == Reg || TRI->regsOverlap(MOReg, Reg);
281 analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI) argument
H A DRegAllocGreedy.cpp112 const TargetRegisterInfo *TRI; member in class:__anon25792::RAGreedy
516 bool ReverseLocal = TRI->reverseLocalAssignment();
517 bool ForceGlobal = !ReverseLocal && TRI->mayOverrideLocalAssignment() &&
585 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
595 unsigned Cost = TRI->getCostPerUse(PhysReg);
601 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
619 MCRegUnitIterator Units(PhysReg, TRI);
632 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI)
695 for (MCRegUnitIterator Units(PhysReg, TRI); Unit
1495 getNumAllocatableRegsForConstraints( const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, const RegisterClassInfo &RCI) argument
[all...]
H A DPrologEpilogInserter.cpp113 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); local
118 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : nullptr;
119 FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(Fn);
165 if (TRI->requiresRegisterScavenging(Fn) && FrameIndexVirtualScavenging)
342 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); local
347 if (!TFI->spillCalleeSavedRegisters(*EntryBlock, I, CSI, TRI)) {
355 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
357 RC, TRI);
380 if (!TFI->restoreCalleeSavedRegisters(*MBB, I, CSI, TRI)) {
383 const TargetRegisterClass *RC = TRI
744 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); local
[all...]
H A DLiveIntervalUnion.cpp82 LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
89 << PrintReg(SI.value()->reg, TRI);
/external/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp143 const TargetRegisterInfo *TRI; member in class:__anon25935::SSACCmpConv
195 TRI = MF.getTarget().getRegisterInfo();
354 MIOperands(I).analyzePhysReg(AArch64::NZCV, TRI);
425 if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {
596 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
605 TII->getRegClass(MCID, 1, TRI, *MF));
652 TII->getRegClass(MCID, 0, TRI, *MF));
655 TII->getRegClass(MCID, 1, TRI, *MF));
725 const TargetRegisterInfo *TRI; member in class:__anon25936::AArch64ConditionalCompares
895 TRI
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp135 RC = TRI->getAllocatableClass(
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
142 TRI->getCommonSubClass(UseRC, RC);
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
221 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
230 VTRC = TRI->getCommonSubClass(RC, VTRC);
331 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
439 const TargetRegisterClass *RC = TRI
[all...]
H A DResourcePriorityQueue.cpp49 TRI = IS->getTargetLowering()->getTargetMachine().getRegisterInfo();
58 unsigned NumRC = TRI->getNumRegClasses();
63 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
64 E = TRI->regclass_end(); I != E; ++I)
65 RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, *IS->MF);
369 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
370 E = TRI->regclass_end(); I != E; ++I) {
376 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
377 E = TRI->regclass_end(); I != E; ++I) {
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUInstrInfo.cpp127 const TargetRegisterInfo *TRI) const {
136 const TargetRegisterInfo *TRI) const {
H A DAMDGPUInstrInfo.h82 const TargetRegisterInfo *TRI) const;
87 const TargetRegisterInfo *TRI) const;
/external/llvm/lib/Target/R600/
H A DAMDGPUInstrInfo.h88 const TargetRegisterInfo *TRI) const override;
93 const TargetRegisterInfo *TRI) const override;

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