Searched refs:getRegister (Results 26 - 50 of 87) sorted by relevance

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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600ExpandSpecialInstrs.cpp126 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
H A DSIAssignInterpRegs.cpp112 unsigned new_reg = AMDGPU::VReg_32RegClass.getRegister(used_vgprs);
H A DR600ISelLowering.cpp100 unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(RegIndex);
150 AMDGPU::R600_TReg32RegClass.getRegister(ReservedIndex);
262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
/external/llvm/include/llvm/MC/
H A DMCWin64EH.h59 unsigned getRegister() const { return Register; } function in class:llvm::MCWin64EHInstruction
H A DMCDwarf.h440 unsigned getRegister() const { function in class:llvm::MCCFIInstruction
H A DMCRegisterInfo.h62 /// getRegister - Return the specified register in the class.
64 unsigned getRegister(unsigned i) const { function in class:llvm::MCRegisterClass
/external/llvm/lib/Target/R600/
H A DSIRegisterInfo.cpp126 return SubRC->getRegister(Index + Channel);
H A DR600EmitClauseMarkers.cpp165 AMDGPU::R600_KC0RegClass.getRegister(UsedKCache[j].second));
169 AMDGPU::R600_KC1RegClass.getRegister(UsedKCache[j].second));
H A DR600InstrInfo.cpp1096 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1099 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1131 case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
1132 case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
1133 case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
1134 case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
1163 case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
1164 case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
1165 case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
1166 case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Addres
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H A DSIInstrInfo.cpp1546 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1564 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1586 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
1589 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
1592 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
1595 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
1598 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
1601 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600ExpandSpecialInstrs.cpp126 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
H A DSIAssignInterpRegs.cpp112 unsigned new_reg = AMDGPU::VReg_32RegClass.getRegister(used_vgprs);
H A DR600ISelLowering.cpp100 unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(RegIndex);
150 AMDGPU::R600_TReg32RegClass.getRegister(ReservedIndex);
262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
/external/smali/dexlib2/src/main/java/org/jf/dexlib2/writer/builder/
H A DBuilderClassPool.java387 startLocal.getRegister(),
395 writer.writeEndLocal(endLocal.getCodeAddress(), endLocal.getRegister());
400 writer.writeRestartLocal(restartLocal.getCodeAddress(), restartLocal.getRegister());
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp402 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
410 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
421 .getRegister(RegIdx.Index / 2);
429 .getRegister(RegIdx.Index);
437 .getRegister(RegIdx.Index);
445 .getRegister(RegIdx.Index);
453 .getRegister(RegIdx.Index);
463 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
471 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
479 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegId
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/external/llvm/lib/Target/Mips/
H A DMipsISelDAGToDAG.cpp62 return CurDAG->getRegister(GlobalBaseReg,
/external/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp122 Reg = CurDAG->getRegister(XCore::CP, MVT::i32);
125 Reg = CurDAG->getRegister(XCore::DP, MVT::i32);
/external/llvm/lib/MC/
H A DMCDwarf.cpp1091 unsigned Reg1 = Instr.getRegister();
1108 unsigned Reg = Instr.getRegister();
1143 Streamer.AddComment(Twine("Reg ") + Twine(Instr.getRegister()));
1144 Streamer.EmitULEB128IntValue(Instr.getRegister());
1161 Streamer.AddComment(Twine("Reg ") + Twine(Instr.getRegister()));
1162 Streamer.EmitULEB128IntValue(Instr.getRegister());
1172 unsigned Reg = Instr.getRegister();
1210 unsigned Reg = Instr.getRegister();
1218 unsigned Reg = Instr.getRegister();
/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp270 Segment = CurDAG->getRegister(0, MVT::i32);
627 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
630 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
695 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
760 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
1327 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1329 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1338 AM.Base_Reg = CurDAG->getRegister(0, VT);
1342 AM.IndexReg = CurDAG->getRegister(0, VT);
1431 Base = CurDAG->getRegister(
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/external/smali/dexlib2/src/main/java/org/jf/dexlib2/writer/pool/
H A DClassPool.java478 startLocal.getRegister(),
486 writer.writeEndLocal(endLocal.getCodeAddress(), endLocal.getRegister());
491 writer.writeRestartLocal(restartLocal.getCodeAddress(), restartLocal.getRegister());
/external/dexmaker/src/dx/java/com/android/dx/dex/code/
H A DLocalList.java267 public int getRegister() { method in class:LocalList.Entry
399 int reg = e.getRegister();
/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h68 /// getRegister - Return the specified register in the class.
70 unsigned getRegister(unsigned i) const { function in class:llvm::TargetRegisterClass
71 return MC->getRegister(i);
/external/llvm/utils/TableGen/
H A DCodeGenInstruction.h326 Record *getRegister() const { assert(isReg()); return R; } function in struct:llvm::CodeGenInstAlias::ResultOperand
/external/llvm/lib/CodeGen/
H A DExecutionDepsFix.cpp521 DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
741 for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true);
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
227 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy()));
308 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
777 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
794 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
827 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
837 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
868 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
913 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
1131 SDValue StackPtr = DAG.getRegister(S
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