Searched refs:Reg (Results 251 - 275 of 321) sorted by relevance

<<111213

/external/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp285 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) { argument
286 if (!LiveOutRegInfo.inBounds(Reg))
289 LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
H A DSelectionDAGBuilder.cpp614 unsigned Reg, Type *Ty) {
622 Regs.push_back(Reg + i);
624 Reg += NumRegs;
841 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
845 assert(Reg < Regs.size() && "Mismatch in # registers expected");
846 unsigned TheReg = Regs[Reg++];
1315 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1316 CopyValueToVirtualRegister(V, Reg);
1726 assert(JT.Reg != -1U && "Should lower JT Header first!");
1729 JT.Reg, PT
613 RegsForValue(LLVMContext &Context, const TargetLowering &tli, unsigned Reg, Type *Ty) argument
[all...]
H A DSelectionDAGISel.cpp470 unsigned Reg = local
472 if (TargetRegisterInfo::isPhysicalRegister(Reg))
475 MachineInstr *Def = RegInfo->getVRegDef(Reg);
482 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
485 // If Reg is live-in then update debug info to track its copy in a vreg.
486 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
911 if (unsigned Reg = TLI->getExceptionPointerRegister())
912 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
915 if (unsigned Reg = TLI->getExceptionSelectorRegister())
916 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrR
1864 unsigned Reg = getTargetLowering()->getRegisterByName( local
1877 unsigned Reg = getTargetLowering()->getRegisterByName( local
[all...]
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp44 bool setATReg(unsigned Reg);
1567 bool MipsAssemblerOptions::setATReg(unsigned Reg) { argument
1568 if (Reg > 31)
1571 aTReg = Reg;
2359 const AsmToken &Reg = Parser.getTok(); local
2360 if (Reg.is(AsmToken::Identifier)) {
2361 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
2362 } else if (Reg.is(AsmToken::Integer)) {
2363 AtRegNo = Reg.getIntVal();
2559 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Reg; local
[all...]
/external/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h60 struct RegOp Reg; member in union:llvm::X86Operand::__anon26166
95 return Reg.RegNo;
427 Res->Reg.RegNo = RegNo;
H A DX86AsmInstrumentation.cpp35 bool IsStackReg(unsigned Reg) { argument
36 return Reg == X86::RSP || Reg == X86::ESP || Reg == X86::SP;
/external/valgrind/main/VEX/priv/
H A Dhost_amd64_defs.h128 Aam_IR, /* Immediate + Reg */
178 } Reg; member in union:__anon31660::__anon31661
213 } Reg; member in union:__anon31666::__anon31667
240 } Reg; member in union:__anon31671::__anon31672
H A Dhost_x86_defs.h116 Xam_IR, /* Immediate + Reg */
166 } Reg; member in union:__anon32142::__anon32143
200 } Reg; member in union:__anon32148::__anon32149
227 } Reg; member in union:__anon32153::__anon32154
/external/llvm/utils/TableGen/
H A DDAGISelMatcher.h878 /// Reg - The def for the register that we're emitting. If this is null, then
880 const CodeGenRegister *Reg; member in class:llvm::EmitRegisterMatcher
884 : Matcher(EmitRegister), Reg(reg), VT(vt) {}
886 const CodeGenRegister *getReg() const { return Reg; }
896 return cast<EmitRegisterMatcher>(M)->Reg == Reg &&
900 return ((unsigned)(intptr_t)Reg) << 4 | VT;
H A DDAGISelMatcher.cpp238 if (Reg)
239 OS << Reg->getName();
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600InstrInfo.cpp349 unsigned Reg = MI->getOperand(idx).getReg(); local
350 switch (Reg) {
/external/clang/lib/CodeGen/
H A DCGValue.h344 static LValue MakeGlobalReg(llvm::Value *Reg, argument
349 R.V = Reg;
/external/llvm/include/llvm/CodeGen/
H A DLiveInterval.h535 LiveInterval(unsigned Reg, float Weight) argument
536 : reg(Reg), weight(Weight) {}
H A DFastISel.h344 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h607 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
811 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
813 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
818 unsigned Reg, MachineRegisterInfo *MRI) const {
884 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg'
897 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true
606 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
817 FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const argument
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp250 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); local
251 MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
/external/llvm/tools/llvm-objdump/
H A DCOFFDump.cpp50 static StringRef getUnwindRegisterName(uint8_t Reg) { argument
51 switch(Reg) {
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600InstrInfo.cpp349 unsigned Reg = MI->getOperand(idx).getReg(); local
350 switch (Reg) {
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h170 unsigned Reg, MachineRegisterInfo *MRI) const override;
/external/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.h73 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
76 /// \returns a RegisterSDNode representing Reg.
79 unsigned Reg, EVT VT) const;
/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h236 // physical register Reg.
239 unsigned Reg, uint64_t Value) const;
/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp219 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo); local
220 Inst.addOperand(MCOperand::CreateReg(Reg));
231 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo); local
232 Inst.addOperand(MCOperand::CreateReg(Reg));
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp688 unsigned Reg = MO.getReg(); local
689 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
690 if (!OpRegCstraints->contains(Reg))
692 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
693 !MRI->constrainRegClass(Reg, OpRegCstraints))
1256 unsigned Reg, unsigned SubIdx,
1260 return MIB.addReg(Reg, State);
1262 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1263 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
1264 return MIB.addReg(Reg, Stat
[all...]
H A DAArch64FastISel.cpp54 unsigned Reg; member in union:__anon25940::AArch64FastISel::Address::__anon25942
60 Address() : Kind(RegBase), Offset(0) { Base.Reg = 0; }
65 void setReg(unsigned Reg) { argument
67 Base.Reg = Reg;
71 return Base.Reg;
1594 unsigned Reg = getRegForValue(RV); local
1595 if (Reg == 0)
1598 unsigned SrcReg = Reg + VA.getValNo();
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1599 unsigned Reg; local
1600 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1601 return Reg;
1621 unsigned Reg; local
1622 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1623 return Reg;
3021 static bool isHReg(unsigned Reg) { argument
3022 return X86::GR8_ABCD_HRegClass.contains(Reg);
3067 inline static bool MaskRegClassContains(unsigned Reg) { argument
3068 return X86::VK8RegClass.contains(Reg) ||
3179 getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI, bool load) argument
3900 unsigned Reg = MO.getReg(); local
3952 unsigned Reg = MIB->getOperand(0).getReg(); local
4228 unsigned Reg = MO.getReg(); local
4310 unsigned Reg = MI->getOperand(OpNum).getReg(); local
4580 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
[all...]

Completed in 1340 milliseconds

<<111213