/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCTargetDesc.cpp | 82 MCCFIInstruction Inst = local 84 MAI->addInitialFrameState(Inst);
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | R600MCCodeEmitter.cpp | 134 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI); local 138 uint64_t ISAOpCode = Inst & (0x3FFULL << 39); 139 Inst &= ~(0x3FFULL << 39); 140 Inst |= ISAOpCode << 1; 142 Emit(Inst, OS);
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCTargetDesc.cpp | 40 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); local 41 MAI->addInitialFrameState(Inst); 49 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047); local 50 MAI->addInitialFrameState(Inst);
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/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmInstrumentation.cpp | 51 const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, 53 InstrumentMOV(Inst, Operands, Ctx, MII, Out); 66 void InstrumentMOV(const MCInst &Inst, OperandVector &Operands, 68 void EmitInstruction(MCStreamer &Out, const MCInst &Inst) { argument 69 Out.EmitInstruction(Inst, STI); 98 const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, 103 switch (Inst.getOpcode()) { 134 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore(); 186 MCInst Inst; local 187 Inst 97 InstrumentMOV( const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) argument 199 MCInst Inst; local 224 MCInst Inst; local 267 MCInst Inst; local 278 MCInst Inst; local 326 MCInst Inst; local 362 MCInst Inst; local 373 MCInst Inst; local 398 MCInst Inst; local 442 MCInst Inst; local 451 MCInst Inst; local 488 InstrumentInstruction( const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) argument [all...] |
/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCTargetDesc.cpp | 288 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( local 290 MAI->addInitialFrameState(Inst);
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/external/llvm/lib/Target/XCore/MCTargetDesc/ |
H A D | XCoreMCTargetDesc.cpp | 61 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, XCore::SP, 0); local 62 MAI->addInitialFrameState(Inst);
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/external/llvm/lib/Transforms/ObjCARC/ |
H A D | ObjCARC.h | 261 static inline Value *GetObjCArg(Value *Inst) { argument 262 return StripPointerCastsAndObjCCalls(cast<CallInst>(Inst)->getArgOperand(0));
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H A D | ObjCARCContract.cpp | 228 Instruction *Inst = I; 229 if (Inst == Release) { 234 InstructionClass Class = GetBasicInstructionClass(Inst); 243 if (CanUse(Inst, Load, PA, Class)) 245 } else if (AA->getModRefInfo(Inst, Loc) & AliasAnalysis::Mod) { 248 Store = dyn_cast<StoreInst>(Inst); 345 Instruction *Inst = &*I++; local 347 DEBUG(dbgs() << "ObjCARCContract: Visiting: " << *Inst << "\n"); 351 InstructionClass Class = GetBasicInstructionClass(Inst); 358 if (ContractAutorelease(F, Inst, Clas [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | LoopRotation.cpp | 383 Instruction *Inst = I++; local 391 if (L->hasLoopInvariantOperands(Inst) && 392 !Inst->mayReadFromMemory() && !Inst->mayWriteToMemory() && 393 !isa<TerminatorInst>(Inst) && !isa<DbgInfoIntrinsic>(Inst) && 394 !isa<AllocaInst>(Inst)) { 395 Inst->moveBefore(LoopEntryBranch); 400 Instruction *C = Inst->clone(); 414 ValueMap[Inst] [all...] |
/external/llvm/lib/Transforms/Utils/ |
H A D | LoopUnroll.cpp | 454 if (Instruction *Inst = 456 RecursivelyDeleteTriviallyDeadInstructions(Inst); 466 Instruction *Inst = I++; local 468 if (isInstructionTriviallyDead(Inst)) 469 (*BB)->getInstList().erase(Inst); 470 else if (Value *V = SimplifyInstruction(Inst)) 471 if (LI->replacementPreservesLCSSAForm(Inst, V)) { 472 Inst->replaceAllUsesWith(V); 473 (*BB)->getInstList().erase(Inst);
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/external/llvm/tools/bugpoint/ |
H A D | CrashDebugger.cpp | 401 Instruction *Inst = I++; local 402 if (!Instructions.count(Inst) && !isa<TerminatorInst>(Inst) && 403 !isa<LandingPadInst>(Inst)) { 404 if (!Inst->getType()->isVoidTy()) 405 Inst->replaceAllUsesWith(UndefValue::get(Inst->getType())); 406 Inst->eraseFromParent();
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/external/llvm/utils/TableGen/ |
H A D | InstrInfoEmitter.cpp | 55 void emitRecord(const CodeGenInstruction &Inst, unsigned Num, 71 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst); 88 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { argument 91 for (auto &Op : Inst.Operands) { 180 for (const CodeGenInstruction *Inst : Target.instructions()) { 181 std::vector<std::string> OperandInfo = GetOperandInfo(*Inst); 208 for (const CodeGenInstruction *Inst : NumberedInstructions) { 209 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable")) 212 for (const auto &Info : Inst->Operands) { 221 OperandMap[OpList].push_back(Namespace + "::" + Inst 362 Record *Inst = II->TheDef; local 461 emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) argument [all...] |
/external/mesa3d/src/gallium/auxiliary/gallivm/ |
H A D | lp_bld_debug.cpp | 295 MCInst Inst; local 305 if (!DisAsm->getInstruction(Inst, Size, memoryObject, 335 Printer->printInst(&Inst, Out, ""); 337 Printer->printInst(&Inst, Out); 339 Printer->printInst(&Inst); 350 const MCInstrDesc &TID = TII->get(Inst.getOpcode()); 352 const TargetInstrDesc &TID = TII->get(Inst.getOpcode()); 360 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) { 361 const MCOperand &operand = Inst.getOperand(i);
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/external/llvm/include/llvm/Analysis/ |
H A D | MemoryDependenceAnalysis.h | 104 static MemDepResult getDef(Instruction *Inst) { argument 105 assert(Inst && "Def requires inst"); 106 return MemDepResult(PairTy(Inst, Def)); 108 static MemDepResult getClobber(Instruction *Inst) { argument 109 assert(Inst && "Clobber requires inst"); 110 return MemDepResult(PairTy(Inst, Clobber)); 182 static MemDepResult getDirty(Instruction *Inst) { argument 183 return MemDepResult(PairTy(Inst, Invalid)); 440 void verifyRemoved(Instruction *Inst) const;
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineModuleInfo.h | 245 addFrameInst(const MCCFIInstruction &Inst) { argument 246 FrameInstructions.push_back(Inst);
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/external/llvm/lib/Analysis/ |
H A D | CostModel.cpp | 527 Instruction *Inst = it; local 528 unsigned Cost = getInstructionCost(Inst); 534 OS << " for instruction: "<< *Inst << "\n"; local
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/external/llvm/lib/CodeGen/ |
H A D | SjLjEHPrepare.cpp | 294 Instruction *Inst = II; local 295 if (Inst->use_empty()) 297 if (Inst->hasOneUse() && 298 cast<Instruction>(Inst->user_back())->getParent() == BB && 299 !isa<PHINode>(Inst->user_back())) 304 if (AllocaInst *AI = dyn_cast<AllocaInst>(Inst)) 310 for (User *U : Inst->users()) { 318 LiveBBs.insert(Inst->getParent()); 329 if (PN->getIncomingValue(i) == Inst) 340 DEBUG(dbgs() << "SJLJ Spill: " << *Inst << " aroun [all...] |
/external/llvm/lib/MC/ |
H A D | MCELFStreamer.cpp | 396 void MCELFStreamer::EmitInstToFragment(const MCInst &Inst, argument 398 this->MCObjectStreamer::EmitInstToFragment(Inst, STI); 405 void MCELFStreamer::EmitInstToData(const MCInst &Inst, argument 411 Assembler.getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64AsmBackend.cpp | 71 bool mayNeedRelaxation(const MCInst &Inst) const override; 75 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override; 224 bool AArch64AsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 239 void AArch64AsmBackend::relaxInstruction(const MCInst &Inst, argument 366 const MCCFIInstruction &Inst = Instrs[i]; variable 368 switch (Inst.getOperation()) { 374 assert(getXRegFromWReg(MRI.getLLVMRegNum(Inst.getRegister(), true)) == 402 StackSize = std::abs(Inst.getOffset()); 408 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true);
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsTargetStreamer.cpp | 587 MCInst Inst; local 592 Inst.setOpcode(Mips::DADDu); 593 Inst.addOperand(MCOperand::CreateReg(RegOrOffset)); 594 Inst.addOperand(MCOperand::CreateReg(Mips::GP)); 595 Inst.addOperand(MCOperand::CreateReg(Mips::ZERO)); 598 Inst.setOpcode(Mips::SD); 599 Inst.addOperand(MCOperand::CreateReg(Mips::GP)); 600 Inst.addOperand(MCOperand::CreateReg(Mips::SP)); 601 Inst.addOperand(MCOperand::CreateImm(RegOrOffset)); 603 getStreamer().EmitInstruction(Inst, ST [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | Mips16HardFloat.cpp | 373 Instruction &Inst = *I; local 407 CallInst::Create(F, Params, "", &Inst );
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUPromoteAlloca.cpp | 136 static bool canVectorizeInst(Instruction *Inst) { argument 137 switch (Inst->getOpcode()) { 200 Instruction *Inst = cast<Instruction>(*I); local 201 IRBuilder<> Builder(Inst); 202 switch (Inst->getOpcode()) { 204 Value *Ptr = Inst->getOperand(0); 209 Inst->replaceAllUsesWith(ExtractElement); 210 Inst->eraseFromParent(); 214 Value *Ptr = Inst->getOperand(1); 219 Inst [all...] |
/external/llvm/lib/Target/Sparc/Disassembler/ |
H A D | SparcDisassembler.cpp | 116 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, argument 123 Inst.addOperand(MCOperand::CreateReg(Reg)); 127 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, argument 134 Inst.addOperand(MCOperand::CreateReg(Reg)); 139 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, argument 146 Inst.addOperand(MCOperand::CreateReg(Reg)); 151 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, argument 158 Inst.addOperand(MCOperand::CreateReg(Reg)); 163 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, argument 173 Inst 177 DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 312 DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument 318 DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument 324 DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument 330 DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument 336 DecodeStoreInt(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument 342 DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument 348 DecodeStoreDFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument 354 DecodeStoreQFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder) argument [all...] |
/external/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 89 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, 94 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, 99 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, 102 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val, 105 static DecodeStatus Decode2RInstruction(MCInst &Inst, 110 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, 115 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, 120 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, 125 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, 130 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, 212 DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 224 DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 236 DecodeBitpOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 247 DecodeNegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 288 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 358 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 371 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 384 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 397 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 411 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 424 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 437 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 451 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 522 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 536 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 550 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 563 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 576 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 589 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 602 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 616 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 631 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 645 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 659 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 679 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 693 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 713 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 732 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineSimplifyDemanded.cpp | 51 /// SimplifyDemandedInstructionBits - Inst is an integer instruction that 54 bool InstCombiner::SimplifyDemandedInstructionBits(Instruction &Inst) { argument 55 unsigned BitWidth = Inst.getType()->getScalarSizeInBits(); 59 Value *V = SimplifyDemandedUseBits(&Inst, DemandedMask, 62 if (V == &Inst) return true; 63 ReplaceInstUsesWith(Inst, V);
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