/external/llvm/lib/CodeGen/ |
H A D | GCStrategy.cpp | 71 const TargetInstrInfo *TII; member in class:__anon25748::GCMachineCodeAnalysis 349 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label); 406 TII = TM->getInstrInfo();
|
H A D | MachineInstrBundle.cpp | 107 const TargetInstrInfo *TII = TM.getInstrInfo(); local 111 TII->get(TargetOpcode::BUNDLE));
|
H A D | MachineRegisterInfo.cpp | 70 const TargetInstrInfo *TII = TM.getInstrInfo(); local 84 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, 366 const TargetInstrInfo &TII) { 381 TII.get(TargetOpcode::COPY), LiveIns[i].second) 364 EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII) argument
|
H A D | SplitKit.h | 48 const TargetInstrInfo &TII; member in class:llvm::SplitAnalysis 217 const TargetInstrInfo &TII; member in class:llvm::SplitEditor
|
H A D | StackSlotColoring.cpp | 51 const TargetInstrInfo *TII; member in class:__anon25827::StackSlotColoring 380 if (TII->isStackSlotCopy(I, FirstSS, SecondSS) && 394 if (!(LoadReg = TII->isLoadFromStackSlot(I, FirstSS))) continue; 395 if (!(StoreReg = TII->isStoreToStackSlot(NextMI, SecondSS))) continue; 425 TII = MF.getTarget().getInstrInfo();
|
H A D | VirtRegMap.cpp | 57 TII = mf.getTarget().getInstrInfo(); 160 const TargetInstrInfo *TII; member in class:__anon25833::VirtRegRewriter 209 TII = TM->getInstrInfo(); 400 MI->setDesc(TII->get(TargetOpcode::KILL));
|
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.cpp | 113 const TargetInstrInfo *TII, 124 const MCInstrDesc &II = TII->get(Def->getMachineOpcode()); 232 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || 263 if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads)) 305 const MCInstrDesc &MCID = TII->get(Opc); 364 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) 382 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) 440 const MCInstrDesc &MCID = TII->get(Opc); 454 TII->get(N->getMachineOpcode()).getImplicitDefs()) { 459 if (NumUsed > TII 111 CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) argument [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 66 const AArch64InstrInfo *TII; member in class:__anon25930::AArch64AdvSIMDScalar 264 static MachineInstr *insertCopy(const AArch64InstrInfo *TII, MachineInstr *MI, argument 267 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AArch64::COPY), 322 insertCopy(TII, MI, Src0, OrigSrc0, true); 327 insertCopy(TII, MI, Src1, OrigSrc1, true); 338 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst) 345 insertCopy(TII, MI, MI->getOperand(0).getReg(), Dst, true); 374 TII = static_cast<const AArch64InstrInfo *>(TM.getInstrInfo());
|
H A D | AArch64BranchRelaxation.cpp | 80 const AArch64InstrInfo *TII; member in class:__anon25932::AArch64BranchRelaxation 168 Size += TII->GetInstSizeInBytes(&MI); 186 Offset += TII->GetInstSizeInBytes(I); 229 BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::B)).addMBB(NewBB); 396 MI->setDesc(TII->get(getOppositeConditionOpcode(MI->getOpcode()))); 408 TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, false); 413 int delta = TII->GetInstSizeInBytes(&MBB->back()); 431 MBB, DebugLoc(), TII->get(getOppositeConditionOpcode(MI->getOpcode()))) 439 BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back()); 440 BuildMI(MBB, DebugLoc(), TII [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.cpp | 43 const TargetInstrInfo &TII, DebugLoc dl, 46 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, 54 const Thumb1InstrInfo &TII = local 75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); 78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); 94 const Thumb1InstrInfo &TII = local 118 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, 123 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 129 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize), 134 BuildMI(MBB, MBBI, dl, TII 41 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, DebugLoc dl, const Thumb1RegisterInfo &MRI, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) argument 326 const Thumb1InstrInfo &TII = local 420 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 459 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local [all...] |
H A D | Thumb1RegisterInfo.cpp | 70 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 76 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci)) 93 const TargetInstrInfo &TII, 115 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) 118 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) 120 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)) 129 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); 169 int NumBytes, const TargetInstrInfo &TII, 229 TII, MRI, MIFlags); 239 const MCInstrDesc &MCID = TII 88 emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags = MachineInstr::NoFlags) argument 165 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags) argument 299 emitThumbConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Imm, const TargetInstrInfo &TII, const Thumb1RegisterInfo& MRI, DebugLoc dl) argument [all...] |
H A D | Thumb2ITBlockPass.cpp | 33 const Thumb2InstrInfo *TII; member in class:__anon26005::Thumb2ITBlockPass 183 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT)) 258 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
|
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.cpp | 118 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 122 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0); 125 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real), 127 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr), 132 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes); 157 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 161 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME)); 162 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::ADD_rr), 183 BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4)); 198 BuildMI(MBB, MBBI, dl, TII 228 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local 283 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | Mips16ISelDAGToDAG.cpp | 74 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 84 BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0). 89 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16); 90 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg) 105 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 109 BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
|
H A D | MipsLongBranch.cpp | 172 const MipsInstrInfo *TII = local 180 MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI); 219 const MipsInstrInfo *TII = local 221 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); 222 const MCInstrDesc &NewDesc = TII->get(NewOpc); 256 const MipsInstrInfo *TII = local 293 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) 295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) 314 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) 317 .append(BuildMI(*MF, DL, TII 437 emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) argument 449 const MipsInstrInfo *TII = local [all...] |
H A D | MipsOptimizePICCall.cpp | 133 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 136 BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
|
/external/llvm/lib/Target/R600/ |
H A D | R600ExpandSpecialInstrs.cpp | 34 const R600InstrInfo *TII; member in class:__anon26116::R600ExpandSpecialInstrsPass 41 TII(nullptr) { } 60 int OpIdx = TII->getOperandIdx(*OldMI, Op); 63 TII->setImmOperand(NewMI, Op, Val); 68 TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo()); 70 const R600RegisterInfo &TRI = TII->getRegisterInfo(); 81 if (TII->isLDSRetInstr(MI.getOpcode())) { 82 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); 85 MachineInstr *Mov = TII->buildMovInstr(&MBB, I, 88 int LDSPredSelIdx = TII [all...] |
H A D | R600OptimizeVectorRegisters.cpp | 87 const R600InstrInfo *TII; member in class:__anon26117::R600VectorRegMerger 111 TII(nullptr) { } 133 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) 195 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG), 212 Pos = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg) 249 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) 317 TII = static_cast<const R600InstrInfo *>(Fn.getTarget().getInstrInfo()); 330 if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
|
H A D | R600Packetizer.cpp | 61 const R600InstrInfo *TII; member in class:__anon26118::R600PacketizerList 76 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) 88 if (TII->isPredicated(BI)) 90 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write); 93 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); 98 if (isTrans || TII->isTransOnly(BI)) { 140 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]); 154 TII (static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo())), 155 TRI(TII->getRegisterInfo()) { 173 if (TII 331 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo(); local [all...] |
H A D | SIInsertWaits.cpp | 49 const SIInstrInfo *TII; member in class:__anon26125::SIInsertWaits 100 TII(nullptr), 125 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags; 137 if (TII->isSMRD(MI.getOpcode())) { 298 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT)) 349 TII = static_cast<const SIInstrInfo*>(MF.getTarget().getInstrInfo());
|
H A D | SILowerControlFlow.cpp | 71 const SIInstrInfo *TII; member in class:__anon26128::SILowerControlFlowPass 96 MachineFunctionPass(ID), TRI(nullptr), TII(nullptr) { } 140 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ)) 159 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) 164 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP)) 176 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)); 185 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) 188 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) 204 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst) 207 BuildMI(MBB, &MI, DL, TII [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | DelaySlotFiller.cpp | 113 const TargetInstrInfo *TII = TM.getInstrInfo(); local 130 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); 148 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); 158 TII->get(SP::UNIMP)).addImm(structSize); 362 const TargetInstrInfo *TII) 377 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr) 389 const TargetInstrInfo *TII) 416 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr) 428 const TargetInstrInfo *TII) 453 RestoreMI->setDesc(TII 360 combineRestoreADD(MachineBasicBlock::iterator RestoreMI, MachineBasicBlock::iterator AddMI, const TargetInstrInfo *TII) argument 387 combineRestoreOR(MachineBasicBlock::iterator RestoreMI, MachineBasicBlock::iterator OrMI, const TargetInstrInfo *TII) argument 426 combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI, MachineBasicBlock::iterator SetHiMI, const TargetInstrInfo *TII) argument 485 const TargetInstrInfo *TII = TM.getInstrInfo(); local [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZFrameLowering.cpp | 130 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); local 174 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG)); 202 TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(), 219 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); local 228 TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(), 244 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG)); 286 const TargetInstrInfo *TII) { 302 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg) 282 emitIncrement(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, unsigned Reg, int64_t NumBytes, const TargetInstrInfo *TII) argument
|
H A D | SystemZLongBranch.cpp | 135 : MachineFunctionPass(ID), TII(nullptr) {} 157 const SystemZInstrInfo *TII; member in class:__anon26159::SystemZLongBranch 212 Terminator.Size = TII->getInstSizeInBytes(MI); 253 TII->getBranchInfo(MI).Target->getMBB()->getNumber(); 283 Block.Size += TII->getInstSizeInBytes(MI); 351 BuildMI(*MBB, MI, DL, TII->get(AddOpcode)) 355 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL)) 360 BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo()); 370 BuildMI(*MBB, MI, DL, TII->get(CompareOpcode)) 373 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FixupLEAs.cpp | 93 const X86InstrInfo *TII; // Machine instruction info. member in class:__anon26188::FixupLEAPass 109 TII->get(MI->getOpcode() == X86::MOV32rr ? X86::LEA32r 147 return TII->convertToThreeAddress(MFI, MBBI, nullptr); 159 TII = static_cast<const X86InstrInfo *>(TM->getInstrInfo()); 221 InstrDistance += TII->getInstrLatency(TM->getInstrItineraryData(), CurInst); 274 !TII->isSafeToClobberEFLAGS(*MFI, I)) 309 NewMI = BuildMI(*MF, MI->getDebugLoc(), TII->get(addrr_opcode)) 319 NewMI = BuildMI(*MF, MI->getDebugLoc(), TII->get(addri_opcode))
|