/external/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 254 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { argument 266 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); 272 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, argument 281 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); 360 unsigned Op1, Op2; local 361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 365 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 373 unsigned Op1, Op2; local 374 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 378 Inst.addOperand(MCOperand::CreateImm(Op1)); 386 unsigned Op1, Op2; local 399 unsigned Op1, Op2; local 413 unsigned Op1, Op2; local 426 unsigned Op1, Op2; local 439 unsigned Op1, Op2; local 524 unsigned Op1, Op2; local 538 unsigned Op1, Op2; local 552 unsigned Op1, Op2, Op3; local 565 unsigned Op1, Op2, Op3; local 578 unsigned Op1, Op2, Op3; local 591 unsigned Op1, Op2, Op3; local 604 unsigned Op1, Op2, Op3; local 618 unsigned Op1, Op2, Op3; local 633 unsigned Op1, Op2, Op3; local 647 unsigned Op1, Op2, Op3; local 661 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local 695 unsigned Op1, Op2, Op3, Op4, Op5; local 715 unsigned Op1, Op2, Op3; local 734 unsigned Op1, Op2, Op3; local [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineMulDivRem.cpp | 121 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 126 if (Value *V = SimplifyMulInst(Op0, Op1, DL)) 132 if (match(Op1, m_AllOnes())) // X * -1 == 0 - X 165 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) { 191 if (isa<Constant>(Op1)) { 206 Value *Mul = Builder->CreateMul(C1, Op1); 210 return BinaryOperator::CreateAdd(Builder->CreateMul(X, Op1), Mul); 216 if (Value *Op1v = dyn_castNegVal(Op1)) 222 Value *Op1C = Op1; 228 BO = dyn_cast<BinaryOperator>(Op1); 435 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 714 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 826 foldUDivPow2Cst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 836 foldUDivNegCst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 845 foldUDivShl(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 867 visitUDivOperand(Value *Op0, Value *Op1, const BinaryOperator &I, SmallVectorImpl<UDivFoldAction> &Actions, unsigned Depth = 0) argument 907 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 969 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1062 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1195 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1227 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1262 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1336 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
H A D | InstCombineShifts.cpp | 26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 34 if (SelectInst *SI = dyn_cast<SelectInst>(Op1)) 38 if (Constant *CUI = dyn_cast<Constant>(Op1)) 46 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) { 50 Op1->getName()); 314 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, argument 319 if (ConstantDataVector *CV = dyn_cast<ConstantDataVector>(Op1)) 321 else if (ConstantVector *CV = dyn_cast<ConstantVector>(Op1)) 324 COp1 = dyn_cast<ConstantInt>(Op1); [all...] |
H A D | InstCombineCompares.cpp | 2286 /// \brief Check if the order of \p Op0 and \p Op1 as operand in an ICmpInst 2293 /// \return true if Op0 and Op1 should be swapped. 2295 const Value * Op1) { 2300 // Count every uses of both Op0 and Op1 in a subtract. 2320 if (BinOp->getOperand(Op1Idx) != Op1) 2329 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 2331 unsigned Op1Cplxity = getComplexity(Op1); 2338 swapMayExposeCSEOpportunities(Op0, Op1))) { 2340 std::swap(Op0, Op1); 2344 if (Value *V = SimplifyICmpInst(I.getPredicate(), Op0, Op1, D 2294 swapMayExposeCSEOpportunities(const Value * Op0, const Value * Op1) argument 2763 Value *Op1 = nullptr, *Op2 = nullptr; local 3503 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
H A D | InstCombineAddSub.cpp | 1452 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1457 if (Value *V = SimplifySubInst(Op0, Op1, I.hasNoSignedWrap(), 1466 if (Value *V = dyn_castNegVal(Op1)) { 1474 return BinaryOperator::CreateXor(Op0, Op1); 1478 return BinaryOperator::CreateNot(Op1); 1483 if (match(Op1, m_Not(m_Value(X)))) 1487 if (SelectInst *SI = dyn_cast<SelectInst>(Op1)) 1493 if (match(Op1, m_Add(m_Value(X), m_Constant(C2)))) 1500 if (C->isNullValue() && match(Op1, m_ZExt(m_Value(X)))) 1502 return CastInst::CreateSExtOrBitCast(X, Op1 1602 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
H A D | InstCombineAndOrXor.cpp | 801 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local 804 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder); 1107 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1112 if (Value *V = SimplifyAndInst(Op0, Op1, DL)) 1124 if (ConstantInt *AndRHS = dyn_cast<ConstantInt>(Op1)) { 1231 if (Value *Op1NotVal = dyn_castNotVal(Op1)) 1232 if (Op0->hasOneUse() && Op1->hasOneUse()) { 1242 match(Op1, m_Not(m_And(m_Value(C), m_Value(D)))) && 1247 if (match(Op1, m_Or(m_Value(A), m_Value(B))) && 1255 Value *tmpOp1 = Op1; 1600 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local 1911 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 2223 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 2458 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local [all...] |
H A D | InstructionCombining.cpp | 216 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(I.getOperand(1)); local 249 if (Op1 && Op1->getOpcode() == Opcode) { 251 Value *B = Op1->getOperand(0); 252 Value *C = Op1->getOperand(1); 291 if (Op1 && Op1->getOpcode() == Opcode) { 293 Value *B = Op1->getOperand(0); 294 Value *C = Op1->getOperand(1); 312 if (Op0 && Op1 528 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS); local 662 Value *Op0 = SO, *Op1 = ConstOperand; local 1328 GetElementPtrInst *Op1 = dyn_cast<GetElementPtrInst>(PN->getOperand(0)); local [all...] |
/external/llvm/lib/Analysis/ |
H A D | InstructionSimplify.cpp | 160 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS)) 161 if (Op1->getOpcode() == OpcodeToExpand) { 163 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1); 197 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS); local 219 if (Op1 && Op1->getOpcode() == Opcode) { 221 Value *B = Op1->getOperand(0); 222 Value *C = Op1->getOperand(1); 261 if (Op1 520 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 576 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 657 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 770 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 779 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 821 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 857 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 885 SimplifyMulInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 948 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 954 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 960 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 968 SimplifyMulInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 976 SimplifyDiv(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1048 SimplifySDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1056 SimplifySDivInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1064 SimplifyUDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1072 SimplifyUDivInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1078 SimplifyFDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned) argument 1091 SimplifyFDivInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1099 SimplifyRem(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1153 SimplifySRemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1161 SimplifySRemInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1169 SimplifyURemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1177 SimplifyURemInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1183 SimplifyFRemInst(Value *Op0, Value *Op1, const Query &, unsigned) argument 1196 SimplifyFRemInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1231 SimplifyShift(unsigned Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1269 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 1285 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1294 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1316 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1326 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1352 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1362 SimplifyAndInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1448 SimplifyAndInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1456 SimplifyOrInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1569 SimplifyOrInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1577 SimplifyXorInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1624 SimplifyXorInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument [all...] |
H A D | ConstantFolding.cpp | 612 /// SymbolicallyEvaluateBinop - One of Op0/Op1 is a constant expression. 617 Constant *Op1, const DataLayout *DL){ 630 computeKnownBits(Op1, KnownZero1, KnownOne1, DL); 636 // All the bits of Op1 that the 'and' could be masking are already zero. 637 return Op1; 654 if (IsConstantOffsetFromGlobal(Op1, GV2, Offs2, *DL) && 1610 if (ConstantFP *Op1 = dyn_cast<ConstantFP>(Operands[0])) { 1613 double Op1V = getValueAsDouble(Op1); 1616 if (Op2->getType() != Op1->getType()) 1624 APFloat V1 = Op1 616 SymbolicallyEvaluateBinop(unsigned Opc, Constant *Op0, Constant *Op1, const DataLayout *DL) argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreSelectionDAGInfo.h | 31 SDValue Op1, SDValue Op2,
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/external/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2, 76 SDValue Op1, SDValue Op2, 92 SDValue Op1, SDValue Op2, 106 SDValue Op1, SDValue Op2, 147 SDValue Op1, SDValue Op2, 57 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 74 EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 90 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument 104 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument 145 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
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/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 54 SDValue Op1, SDValue Op2,
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/external/llvm/include/llvm/CodeGen/ |
H A D | FastISel.h | 201 unsigned Op1, bool Op1IsKill); 228 unsigned Op1, bool Op1IsKill, 272 unsigned Op1, bool Op1IsKill); 279 unsigned Op1, bool Op1IsKill, 307 unsigned Op1, bool Op1IsKill, 315 unsigned Op1, bool Op1IsKill,
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H A D | ISDOpcodes.h | 833 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 839 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
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H A D | SelectionDAG.h | 606 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, argument 611 Ops.push_back(Op1); 855 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2); 856 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 858 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 860 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 869 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT, SDValue Op1); 871 SDValue Op1, SDValue Op2); 873 SDValue Op1, SDValue Op2, SDValue Op3); 884 EVT VT2, SDValue Op1); [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 202 SDValue Op0, Op1; local 206 if (!SelectADDRrr(Op, Op0, Op1)) 207 SelectADDRri(Op, Op0, Op1); 212 OutOps.push_back(Op1);
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/external/llvm/lib/Transforms/Scalar/ |
H A D | Scalarizer.cpp | 74 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 76 return Builder.CreateFCmp(FCI.getPredicate(), Op0, Op1, Name); 85 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 87 return Builder.CreateICmp(ICI.getPredicate(), Op0, Op1, Name); 96 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 98 return Builder.CreateBinOp(BO.getOpcode(), Op0, Op1, Name); 371 Scatterer Op1 = scatter(&I, I.getOperand(1)); local 373 assert(Op1.size() == NumElems && "Mismatched binary operation"); 377 Res[Elem] = Split(Builder, Op0[Elem], Op1[Elem], 390 Scatterer Op1 local 538 Scatterer Op1 = scatter(&SVI, SVI.getOperand(1)); local [all...] |
H A D | CorrelatedValuePropagation.cpp | 169 Constant *Op1 = dyn_cast<Constant>(C->getOperand(1)); 170 if (!Op1) return false; 176 C->getOperand(0), Op1, *PI, C->getParent()); 182 C->getOperand(0), Op1, *PI, C->getParent());
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 386 unsigned Op1 = getRegForValue(I->getOperand(1)); local 387 if (Op1 == 0) return false; 391 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, 447 unsigned Op1 = getRegForValue(I->getOperand(1)); local 448 if (Op1 == 0) 458 Op1, Op1IsKill); 1245 unsigned /*Op1*/, bool /*Op1IsKill*/) { 1275 unsigned /*Op1*/, bool /*Op1IsKill*/, 1376 unsigned Op1, bool Op1IsKill) { 1381 Op1 1373 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 1397 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 1497 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 1524 FastEmitInst_rrii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm1, uint64_t Imm2) argument [all...] |
H A D | LegalizeVectorOps.cpp | 671 SDValue Op1 = Op.getOperand(1); local 675 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); 707 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); 714 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask); 716 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); 848 SDValue Op1 = Op.getOperand(1); local 863 TLI.getBooleanContents(Op1.getValueType()) != 870 if (VT.getSizeInBits() != Op1 [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 173 ICToken Op1 = OperandStack.pop_back_val(); local 179 Val = Op1.second + Op2.second; 183 Val = Op1.second - Op2.second; 187 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 189 Val = Op1.second * Op2.second; 193 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 196 Val = Op1.second / Op2.second; 200 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && 202 Val = Op1.second | Op2.second; 206 assert (Op1 810 doSrcDstMatch(X86Operand &Op1, X86Operand &Op2) argument 2134 X86Operand &Op1 = static_cast<X86Operand &>(*Operands[2]); local 2139 X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]); local 2149 X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]); local [all...] |
/external/llvm/include/llvm/Analysis/ |
H A D | InstructionSimplify.h | 134 Value *SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, 141 Value *SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, 148 Value *SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact,
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/external/llvm/lib/Target/X86/ |
H A D | X86FloatingPoint.cpp | 1168 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 1170 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); 1177 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 1185 moveToTop(Op1, I); 1186 TOS = Op1; 1208 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) && 1215 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0); 1233 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0; 1241 if (KillsOp0 && KillsOp1 && Op0 != Op1) { 1266 unsigned Op1 [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 396 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects 397 // between the base and index. Try to fold Op1 into AM's displacement. 399 SDValue Op0, uint64_t Op1) { 401 int64_t TestDisp = AM.Disp + Op1; 423 SDValue Op1 = N.getOperand(1); local 426 unsigned Op1Code = Op1->getOpcode(); 429 return expandAdjDynAlloc(AM, IsBase, Op1); 434 return expandDisp(AM, IsBase, Op1, 438 cast<ConstantSDNode>(Op1)->getSExtValue()); 440 if (IsBase && expandIndex(AM, Op0, Op1)) 398 expandDisp(SystemZAddressingMode &AM, bool IsBase, SDValue Op0, uint64_t Op1) argument 1094 SDValue Op1 = Node->getOperand(1); local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 416 SDValue Op1 = N->getOperand(1); local 421 CurDAG->computeKnownBits(Op1, RKZ, RKO); 428 unsigned Op1Opc = Op1.getOpcode(); 438 if (Op1.getOperand(0).getOpcode() != ISD::SHL && 439 Op1.getOperand(0).getOpcode() != ISD::SRL) { 440 std::swap(Op0, Op1); 446 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && 447 Op1.getOperand(0).getOpcode() != ISD::SRL) { 448 std::swap(Op0, Op1); 459 isInt32Immediate(Op1 1354 SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1), local [all...] |