| /external/llvm/include/llvm/CodeGen/ |
| H A D | TargetSchedule.h | 35 MCSchedModel SchedModel; member in class:llvm::TargetSchedModel
67 const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
82 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
85 unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
93 return SchedModel.getNumProcResourceKinds();
98 return SchedModel.getProcResource(PIdx);
105 return SchedModel.getProcResource(PIdx)->Name;
140 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
145 return SchedModel.getProcResource(PIdx)->BufferSize;
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| H A D | ScheduleDAGInstrs.h | 86 TargetSchedModel SchedModel; member in class:llvm::ScheduleDAGInstrs
171 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
175 if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
176 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
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| H A D | MachineScheduler.h | 548 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
564 const TargetSchedModel *SchedModel; member in class:llvm::SchedBoundary
634 DAG(nullptr), SchedModel(nullptr), Rem(nullptr), Available(ID, Name+".A"),
683 return RetiredMOps * SchedModel->getMicroOpFactor();
691 return std::max(CurrCycle * SchedModel->getLatencyFactor(),
822 const TargetSchedModel *SchedModel);
827 const TargetSchedModel *SchedModel; member in class:llvm::GenericSchedulerBase
833 Context(C), SchedModel(nullptr), TRI(nullptr) {}
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| H A D | MachineTraceMetrics.h | 73 TargetSchedModel SchedModel; member in class:llvm::MachineTraceMetrics
111 /// This is an array with SchedModel.getNumProcResourceKinds() entries.
114 /// These numbers have already been scaled by SchedModel.getResourceFactor().
364 // where Kinds = SchedModel.getNumProcResourceKinds().
373 unsigned Factor = SchedModel.getLatencyFactor();
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| /external/llvm/lib/CodeGen/ |
| H A D | TargetSchedule.cpp | 32 return EnableSchedModel && SchedModel.hasInstrSchedModel();
57 SchedModel = sm;
62 unsigned NumRes = SchedModel.getNumProcResourceKinds();
64 ResourceLCM = SchedModel.IssueWidth;
66 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
70 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
72 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
107 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
118 SCDesc = SchedModel.getSchedClassDesc(SchedClass);
160 return TII->defaultDefLatency(&SchedModel, DefM
[all...] |
| H A D | MachineTraceMetrics.cpp | 61 SchedModel.init(*ST.getSchedModel(), &ST, TII);
64 SchedModel.getNumProcResourceKinds());
97 unsigned PRKinds = SchedModel.getNumProcResourceKinds();
108 if (!SchedModel.hasInstrSchedModel())
110 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI);
115 PI = SchedModel.getWriteProcResBegin(SC),
116 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
127 PRCycles[K] * SchedModel.getResourceFactor(K);
136 unsigned PRKinds = SchedModel.getNumProcResourceKinds();
150 unsigned PRKinds = MTM.SchedModel
[all...] |
| H A D | MachineScheduler.cpp | 1597 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) { argument
1599 if (!SchedModel->hasInstrSchedModel())
1601 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
1605 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC)
1606 * SchedModel->getMicroOpFactor();
1608 PI = SchedModel->getWriteProcResBegin(SC),
1609 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1611 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1621 SchedModel = smodel;
1623 if (SchedModel
2108 initResourceDelta(const ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) argument
[all...] |
| H A D | ScoreboardHazardRecognizer.cpp | 80 // A nonempty itinerary must have a SchedModel.
81 IssueWidth = ItinData->SchedModel->IssueWidth;
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| H A D | ScheduleDAGInstrs.cpp | 67 SchedModel.init(*ST.getSchedModel(), &ST, TII);
283 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
322 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
401 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
446 dep.setLatency(SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx));
701 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
711 if (SchedModel.hasInstrSchedModel()) {
714 PI = SchedModel.getWriteProcResBegin(SC),
715 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
716 switch (SchedModel
[all...] |
| H A D | TargetInstrInfo.cpp | 749 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel, argument
754 return SchedModel->LoadLatency;
756 return SchedModel->HighLatency;
809 return defaultDefLatency(ItinData->SchedModel, DefMI);
852 defaultDefLatency(ItinData->SchedModel, DefMI));
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| H A D | EarlyIfConversion.cpp | 583 const MCSchedModel *SchedModel; member in class:__anon25740::EarlyIfConverter
691 unsigned CritLimit = SchedModel->MispredictPenalty/2;
787 SchedModel =
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| H A D | IfConversion.cpp | 159 TargetSchedModel SchedModel; member in class:__anon25750::IfConverter
280 SchedModel.init(*ST.getSchedModel(), &ST, TII);
687 unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false);
1585 unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false);
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonMachineScheduler.h | 47 const TargetSchedModel *SchedModel; member in class:llvm::VLIWResourceModel
58 SchedModel(SM), TotalPackets(0) {
65 Packet.resize(SchedModel->getIssueWidth());
135 const TargetSchedModel *SchedModel; member in struct:llvm::ConvergingVLIWScheduler::VLIWSchedBoundary
156 DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"),
169 SchedModel = smodel;
192 const TargetSchedModel *SchedModel; member in class:llvm::ConvergingVLIWScheduler
207 : DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"),
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| H A D | HexagonMachineScheduler.cpp | 130 if (Packet.size() >= SchedModel->getIssueWidth()) {
200 SchedModel = DAG->getSchedModel();
202 Top.init(DAG, SchedModel);
203 Bot.init(DAG, SchedModel);
276 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
277 if (IssueCount + uops > SchedModel->getIssueWidth())
299 unsigned Width = SchedModel->getIssueWidth();
342 IssueCount += SchedModel->getNumMicroOps(SU->getInstr());
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| /external/llvm/include/llvm/MC/ |
| H A D | MCInstrItineraries.h | 113 const MCSchedModel *SchedModel; ///< Basic machine properties. member in class:llvm::InstrItineraryData
121 InstrItineraryData() : SchedModel(&MCSchedModel::DefaultSchedModel),
127 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F),
128 Itineraries(SchedModel->InstrItineraries) {}
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 34 TargetSchedModel SchedModel; member in class:__anon25948::AArch64StorePairSuppress
84 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx);
126 SchedModel.init(*ST.getSchedModel(), &ST, TII);
133 if (!SchedModel.hasInstrSchedModel()) {
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| H A D | AArch64ConditionalCompares.cpp | 726 const MCSchedModel *SchedModel; member in class:__anon25936::AArch64ConditionalCompares
848 unsigned DelayLimit = SchedModel->MispredictPenalty * 3 / 4;
896 SchedModel =
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| /external/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 102 assert(Found->Value && "Missing processor SchedModel value");
108 const MCSchedModel *SchedModel = getSchedModelForCPU(CPU); local
109 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
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| /external/llvm/include/llvm/Target/ |
| H A D | TargetSubtargetInfo.h | 55 const TargetSchedModel* SchedModel) const {
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| H A D | TargetInstrInfo.h | 874 unsigned defaultDefLatency(const MCSchedModel *SchedModel,
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMSubtarget.cpp | 263 SchedModel = getSchedModelForCPU(CPUString);
418 return SchedModel->MispredictPenalty;
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| H A D | ARMSubtarget.h | 227 /// SchedModel - Processor specific instruction costs.
228 const MCSchedModel *SchedModel; member in class:llvm::ARMSubtarget
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ResourcePriorityQueue.cpp | 322 if (Packet.size() >= InstrItins->SchedModel->IssueWidth) {
|