Searched defs:SU (Results 1 - 23 of 23) sorted by path

/external/clang/lib/StaticAnalyzer/Core/
H A DSimpleConstraintManager.h25 SubEngine *SU; member in class:clang::ento::SimpleConstraintManager
29 : SU(subengine), SVB(SB) {}
/external/eigen/blas/
H A Dsrotmg.f55 + SQ2,STEMP,SU,TWO,ZERO local in subroutine:SROTMG
86 SU = ONE - SH12*SH21
88 IF (.NOT.SU.LE.ZERO) GO TO 30
93 SD1 = SD1/SU
94 SD2 = SD2/SU
95 SX1 = SX1*SU
106 SU = ONE + SH11*SH22
107 STEMP = SD2/SU
108 SD2 = SD1/SU
110 SX1 = SY1*SU
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/external/llvm/include/llvm/CodeGen/
H A DMachineScheduler.h200 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
204 virtual void releaseTopNode(SUnit *SU) = 0;
207 virtual void releaseBottomNode(SUnit *SU) = 0;
281 /// \brief Add a DAG edge to the given SU with the given predecessor
325 void updateQueues(SUnit *SU, bool IsTopNode);
339 void releaseSucc(SUnit *SU, SDep *SuccEdge);
340 void releaseSuccessors(SUnit *SU);
341 void releasePred(SUnit *SU, SDep *PredEdge);
342 void releasePredecessors(SUnit *SU);
358 // Map each SU t
412 getPressureDiff(const SUnit *SU) argument
504 find(SUnit *SU) argument
508 push(SUnit *SU) argument
790 SUnit *SU; member in struct:llvm::GenericSchedulerBase::SchedCandidate
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H A DScheduleDAG.h165 void setSUnit(SUnit *SU) { argument
166 Dep.setPointer(SU);
507 virtual void addNode(const SUnit *SU) = 0;
508 virtual void updateNode(const SUnit *SU) = 0;
531 virtual void remove(SUnit *SU) = 0;
578 const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
579 if (SU->isInstr()) return &SU->getInstr()->getDesc();
580 return getNodeDesc(SU->getNode());
589 virtual void dumpNode(const SUnit *SU) cons
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H A DScheduleDAGInstrs.h36 SUnit *SU; member in struct:llvm::VReg2SUnit
38 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
48 SUnit *SU; member in struct:llvm::PhysRegSUOper
52 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
174 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
175 if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
176 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
177 return SU->SchedClass;
233 void dumpNode(const SUnit *SU) cons
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/external/llvm/lib/CodeGen/
H A DCriticalAntiDepBreaker.cpp132 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
134 static const SDep *CriticalPathStep(const SUnit *SU) { argument
138 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
464 const SUnit *SU = &SUnits[i]; local
465 MISUnitMap[SU->getInstr()] = SU;
466 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
467 Max = SU;
669 const SUnit *SU = MISUnitMap[Q->second->getParent()]; local
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H A DDFAPacketizer.cpp167 // Generate MI -> SU map.
170 SUnit *SU = &VLIWScheduler->SUnits[i]; local
171 MIToSUnit[SU->getInstr()] = SU;
H A DLatencyPriorityQueue.cpp55 /// of SU, return it, otherwise return null.
56 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { argument
58 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
73 void LatencyPriorityQueue::push(SUnit *SU) { argument
77 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
79 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
82 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking;
84 Queue.push_back(SU);
92 scheduledNode(SUnit *SU) argument
105 AdjustPriorityOfUnscheduledPreds(SUnit *SU) argument
134 remove(SUnit *SU) argument
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H A DMachineScheduler.cpp520 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { argument
537 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However,
539 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency())
540 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency();
547 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
548 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { argument
549 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
551 releaseSucc(SU, &*I);
559 void ScheduleDAGMI::releasePred(SUnit *SU, SDe argument
587 releasePredecessors(SUnit *SU) argument
724 SUnit *SU = &(*I); local
772 updateQueues(SUnit *SU, bool IsTopNode) argument
908 updateScheduledPressure(const SUnit *SU, const std::vector<unsigned> &NewMaxPressure) argument
961 SUnit *SU = UI->SU; local
1169 scheduleMI(SUnit *SU, bool IsTopNode) argument
1223 SUnit *SU; member in struct:__anon25770::LoadClusterMutation::LoadInfo
1251 SUnit *SU = Loads[Idx]; local
1299 SUnit *SU = &DAG->SUnits[Idx]; local
1349 SUnit *SU = &DAG->SUnits[--Idx]; local
1546 SUnit *SU = &DAG->SUnits[Idx]; local
1636 getLatencyStallCycles(SUnit *SU) argument
1673 checkHazard(SUnit *SU) argument
1753 releaseNode(SUnit *SU, unsigned ReadyCycle) argument
1779 releaseTopNode(SUnit *SU) argument
1786 releaseBottomNode(SUnit *SU) argument
1876 bumpNode(SUnit *SU) argument
2015 SUnit *SU = *(Pending.begin()+i); local
2036 removeReady(SUnit *SU) argument
2495 getWeakLeft(const SUnit *SU, bool isTop) argument
2506 biasPhysRegCopy(const SUnit *SU, bool isTop) argument
2764 SUnit *SU; local
2804 reschedulePhysRegCopies(SUnit *SU, bool isTop) argument
2836 schedNode(SUnit *SU, bool IsTopNode) argument
2968 SUnit *SU; local
2993 schedNode(SUnit *SU, bool IsTopNode) argument
3072 SUnit *SU = ReadyQ.back(); variable
3159 SUnit *SU; variable
3248 getNodeLabel(const SUnit *SU, const ScheduleDAG *G) argument
3259 getNodeDescription(const SUnit *SU, const ScheduleDAG *G) argument
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H A DPostRASchedulerList.cpp175 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
176 void ReleaseSuccessors(SUnit *SU);
177 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
240 if (SUnit *SU = Sequence[i])
241 SU->dump(this);
421 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) { argument
440 // SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
455 /// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors.
456 void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) { argument
457 for (SUnit::succ_iterator I = SU
466 ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) argument
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H A DScheduleDAGInstrs.cpp207 /// the exit SU to the register defs and use list. This is because we want to
250 /// MO is an operand of SU's instruction that defines a physical register. Add
251 /// data dependencies from SU to any uses of the physical register.
252 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { argument
253 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
264 SUnit *UseSU = I->SU;
265 if (UseSU == SU)
274 Dep = SDep(SU, SDep::Artificial);
278 SU->hasPhysRegDefs = true;
279 Dep = SDep(SU, SDe
295 addPhysRegDeps(SUnit *SU, unsigned OperIdx) argument
376 addVRegDefDeps(SUnit *SU, unsigned OperIdx) argument
414 addVRegUseDeps(SUnit *SU, unsigned OperIdx) argument
621 adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI, SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList, unsigned LatencyToLoad) argument
694 SUnit *SU = newSUnit(MI); local
798 SUnit *SU = MISUnitMap[MI]; local
1261 visitPreorder(const SUnit *SU) argument
1269 visitPostorderNode(const SUnit *SU) argument
1421 follow(const SUnit *SU) argument
1441 hasDataSucc(const SUnit *SU) argument
1459 const SUnit *SU = &*SI; local
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H A DScheduleDAGPrinter.cpp78 std::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU, argument
80 return G->getGraphNodeLabel(SU);
H A DScoreboardHazardRecognizer.cpp119 ScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument
129 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
166 DEBUG(dbgs() << "SU(" << SU->NodeNum << "): ");
167 DEBUG(DAG->dumpNode(SU));
179 void ScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) { argument
185 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp72 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { argument
74 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
109 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, argument
112 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
147 static unsigned numberCtrlDepsInSU(SUnit *SU) { argument
149 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
157 static unsigned numberCtrlPredInSU(SUnit *SU) { argument
175 SUnit *SU = &(*SUnits)[i]; local
217 getSingleUnscheduledPred(SUnit *SU) argument
233 push(SUnit *SU) argument
248 isResourceAvailable(SUnit *SU) argument
291 reserveResources(SUnit *SU) argument
328 rawRegPressureDelta(SUnit *SU, unsigned RCId) argument
362 regPressureDelta(SUnit *SU, bool RawPressure) argument
403 SUSchedulingCost(SUnit *SU) argument
473 scheduledNode(SUnit *SU) argument
549 initNumRegDefsLeft(SUnit *SU) argument
581 adjustPriorityOfUnscheduledPreds(SUnit *SU) argument
634 remove(SUnit *SU) argument
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H A DScheduleDAGFast.cpp86 /// AddPred - adds a predecessor edge to SUnit SU.
88 void AddPred(SUnit *SU, const SDep &D) { argument
89 SU->addPred(D);
92 /// RemovePred - removes a predecessor edge from SUnit SU.
94 void RemovePred(SUnit *SU, const SDep &D) { argument
95 SU->removePred(D);
99 void ReleasePred(SUnit *SU, SDep *PredEdge);
100 void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
140 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { argument
161 void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigne argument
183 ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) argument
213 CopyAndMoveSuccessors(SUnit *SU) argument
388 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument
449 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI) argument
470 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) argument
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H A DScheduleDAGRRList.cpp186 /// IsReachable - Checks if SU is reachable from TargetSU.
187 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { argument
188 return Topo.IsReachable(SU, TargetSU);
191 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
193 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { argument
194 return Topo.WillCreateCycle(SU, TargetSU);
197 /// AddPred - adds a predecessor edge to SUnit SU.
200 void AddPred(SUnit *SU, const SDep &D) { argument
201 Topo.AddPred(SU, D.getSUnit());
202 SU
208 RemovePred(SUnit *SU, const SDep &D) argument
214 isReady(SUnit *SU) argument
366 ReleasePred(SUnit *SU, const SDep *PredEdge) argument
526 ReleasePredecessors(SUnit *SU) argument
623 AdvancePastStalls(SUnit *SU) argument
665 EmitNode(SUnit *SU) argument
707 ScheduleNodeBottomUp(SUnit *SU) argument
806 UnscheduleNodeBottomUp(SUnit *SU) argument
895 SUnit *SU = *I; local
905 BacktrackBottomUp(SUnit *SU, SUnit *BtSU) argument
927 isOperandOf(const SUnit *SU, SDNode *N) argument
938 CopyAndMoveSuccessors(SUnit *SU) argument
1137 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument
1207 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI) argument
1229 CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs) argument
1257 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) argument
1333 SUnit *SU = Interferences[i-1]; local
1504 SUnit *SU = PickNodeToScheduleBottomUp(); local
1793 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); variable
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H A DScheduleDAGSDNodes.cpp79 SUnit *SU = &SUnits.back(); local
84 SU->SchedulingPref = Sched::None;
86 SU->SchedulingPref = TLI.getSchedulingPreference(N);
87 return SU;
91 SUnit *SU = newSUnit(Old->getNode()); local
92 SU->OrigNode = Old->OrigNode;
93 SU->Latency = Old->Latency;
94 SU->isVRegCycle = Old->isVRegCycle;
95 SU->isCall = Old->isCall;
96 SU
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H A DScheduleDAGVLIW.cpp88 void releaseSucc(SUnit *SU, const SDep &D);
89 void releaseSuccessors(SUnit *SU);
90 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
117 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { argument
132 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
141 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { argument
143 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
148 releaseSucc(SU, *I);
155 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigne argument
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/external/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp35 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument
38 MachineInstr *MI = SU->getInstr();
76 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
85 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) { argument
86 MachineInstr *MI = SU->getInstr();
92 ScoreboardHazardRecognizer::EmitInstruction(SU);
/external/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp38 /// Check if scheduling of this SU is possible
43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { argument
44 if (!SU || !SU->getInstr())
49 switch (SU->getInstr()->getOpcode()) {
51 if (!ResourcesModel->canReserveResources(SU->getInstr()))
75 if (I->getSUnit() == SU)
83 bool VLIWResourceModel::reserveResources(SUnit *SU) { argument
86 if (!SU) {
92 // If this SU doe
223 releaseTopNode(SUnit *SU) argument
240 releaseBottomNode(SUnit *SU) argument
272 checkHazard(SUnit *SU) argument
283 releaseNode(SUnit *SU, unsigned ReadyCycle) argument
324 bumpNode(SUnit *SU) argument
362 SUnit *SU = *(Pending.begin()+i); local
382 removeReady(SUnit *SU) argument
411 traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, PressureChange P) argument
426 getSingleUnscheduledPred(SUnit *SU) argument
444 getSingleUnscheduledSucc(SUnit *SU) argument
469 SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) argument
644 SUnit *SU; local
686 schedNode(SUnit *SU, bool IsTopNode) argument
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H A DHexagonMachineScheduler.h87 bool isResourceAvailable(SUnit *SU);
88 bool reserveResources(SUnit *SU);
115 SUnit *SU; member in struct:llvm::ConvergingVLIWScheduler::SchedCandidate
123 SchedCandidate(): SU(nullptr), SCost(0) {}
176 bool checkHazard(SUnit *SU);
178 void releaseNode(SUnit *SU, unsigned ReadyCycle);
182 void bumpNode(SUnit *SU);
186 void removeReady(SUnit *SU);
214 virtual void schedNode(SUnit *SU, bool IsTopNode) override;
216 virtual void releaseTopNode(SUnit *SU) overrid
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/external/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp26 bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) { argument
28 if (isBCTRAfterSet(SU))
31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
38 // SU is a load; for any predecessors in this dispatch group, that are stores,
40 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) {
41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
45 if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier())
49 if (SU->Preds[i].getSUnit() == CurGroup[j])
56 bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) { argument
141 getHazardType(SUnit *SU, int Stalls) argument
148 ShouldPreferAnother(SUnit *SU) argument
157 PreEmitNoops(SUnit *SU) argument
175 EmitInstruction(SUnit *SU) argument
325 getHazardType(SUnit *SU, int Stalls) argument
385 EmitInstruction(SUnit *SU) argument
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/external/llvm/lib/Target/R600/
H A DR600MachineScheduler.cpp60 SUnit *SU = nullptr; local
96 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
99 SU = pickAlu();
100 if (!SU && !PhysicalRegCopy.empty()) {
101 SU = PhysicalRegCopy.front();
104 if (SU) {
111 if (!SU) {
113 SU = pickOther(IDFetch);
114 if (SU)
119 if (!SU) {
142 schedNode(SUnit *SU, bool IsTopNode) argument
190 releaseTopNode(SUnit *SU) argument
194 releaseBottomNode(SUnit *SU) argument
294 getInstKind(SUnit* SU) argument
323 SUnit *SU = *It; local
433 SUnit *SU = AttemptFillSlot(3, true); local
442 SUnit *SU = AttemptFillSlot(Chan, false); local
456 SUnit *SU = nullptr; local
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