| bfae8650ec25d9f03ed1f58435325fd9b62b8da8 |
|
26-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Move depth resolve for span fallbacks to a simpler place.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 46751edca9a95baff81771aa69986fa6e2422ed6 |
|
22-Aug-2012 |
Brian Paul <brianp@vmware.com> |
mesa: new _mesa_num_tex_faces() helper
Not a real big help now, but will be useful for the
GL_ARB_texture_cube_map_array extension in the future.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 1bd4d456cdecf7bea55f4e3dac574af54efad994 |
|
04-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Add an enum to describe MSAA layout.
From the Ivy Bridge PRM, Vol 1 Part 1, p112:
There are three types of multisampled surface layouts designated
as follows:
- IMS Interleaved Multisampled Surface
- CMS Compressed Mulitsampled Surface
- UMS Uncompressed Multisampled Surface
Previously, the i965 driver only used IMS and UMS formats, and
distinguished beetween them using the boolean
intel_mipmap_tree::msaa_is_interleaved. To facilitate adding support
for the CMS format, this patch replaces that boolean (and other
booleans derived from it) with an enum
INTEL_MSAA_LAYOUT_{IMS,CMS,UMS}. It also updates the terminology used
in comments throughout the driver to match the IMS/CMS/UMS terminology
used in the PRM. CMS layout is not yet used.
The enum has a fourth possible value, INTEL_MSAA_LAYOUT_NONE, which is
used for non-multisampled surfaces.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 455ac562722f60ac9fb0c3d3c697fa339fa011ad |
|
08-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Properly handle sliced layout for Gen7.
Starting in Gen7, there are two possible layouts for MSAA surfaces:
- Interleaved, in which additional samples are accommodated by scaling
up the width and height of the surface. This is the only layout
available in Gen6. On Gen7 it is used for depth and stencil
surfaces only.
- Sliced, in which the surface is stored as a 2D array, with array
slice n containing all pixel data for sample n. On Gen7 this layout
is used for color surfaces.
The "Sliced" layout has an additional requirement: it must be used in
ARYSPC_LOD0 mode, which means that the surface doesn't leave any extra
room between array slices for miplevels other than 0.
This patch modifies the surface allocation functions to use the
correct layout when allocating MSAA surfaces in Gen7, and to set the
array offsets properly when using ARYSPC_LOD0 mode. It also modifies
the code that populates SURFACE_STATE structures to ensure that
ARYSPC_LOD0 mode is selected in the appropriate circumstances.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 19e9b24626c2b9d7abef054d57bb2a52106c545b |
|
30-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6: Initial implementation of MSAA.
This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to
understand multisampled buffers, adapting the rendering pipeline setup
to enable multisampled rendering, and adding multisample resolve
operations to brw_blorp_blit.cpp. Some preparation work is also
included for Gen7, but it is not yet enabled.
MSAA support is still fairly preliminary. In particular, the
following are not yet supported:
- Fully general blits between MSAA and non-MSAA buffers.
- Formats other than RGBA8, DEPTH24, and STENCIL8.
- Centroid interpolation.
- Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE,
GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE,
GL_SAMPLE_COVERAGE_INVERT).
Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on
i965/Gen6.
v2:
- In intel_alloc_renderbuffer_storage(), quantize the requested number
of samples to the next higher sample count supported by the
hardware. This ensures that a query of GL_SAMPLES will return the
correct value. It also ensures that MSAA is fully disabled on Gen7
for now (since Gen7 MSAA support doesn't work yet).
- When reading from a non-MSAA surface, ensure that s_is_zero is true
so that we won't try to read from a nonexistent sample.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| a07cf3397e332388d3599c83e50ac45511972890 |
|
27-Mar-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add support for sampling texture buffer objects on gen7+.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| f4a93e0665881dd58a95abb6525676bd1cc2e6af |
|
17-Mar-2012 |
Brian Paul <brianp@vmware.com> |
mesa: rework texture completeness testing
Instead of gl_texture_object::_Complete there are now two fields:
_BaseComplete and _MipmapComplete. The former indicates whether the base
texture level is valid. The later indicates whether the whole mipmap is
valid.
With sampler objects, a single texture can appear to be both complete and
incomplete at the same time. See the GL_ARB_sampler_objects spec for more
details. To implement this we now check if the texture is complete with
respect to a sampler state.
Another benefit of this is we no longer need to invalidate a texture's
completeness state when we change the minification/magnification filters
with glTexParameter().
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| e2dce7f7ee3e7da9cbb0bb33307ecd79e824426d |
|
10-Feb-2012 |
Eric Anholt <eric@anholt.net> |
intel: Fix rendering from textures after RenderTexture().
There's a serious trap for drivers: RenderTexture() does not indicate
that the texture is currently bound to the draw buffer, despite
FinishRenderTexture() signaling that the texture is just now being
unbound from the draw buffer.
We were acting as if RenderTexture() *was* the start of rendering and
that we could make texturing incoherent with the current contents of
the renderbuffer. This caused intel oglconform sRGB
Mipmap.1D_textures to fail, because we got a call to TexImage() and
thus RenderTexture() on a texture bound to a framebuffer that wasn't
the draw buffer, so we skipped validating the new image into the
texture object used for rendering.
We can't (easily) make RenderTexture() indicate the start of drawing,
because both our driver and gallium are using it as the moment to set
up the renderbuffer wrapper used for things like MapRenderbuffer().
Instead, postpone the setup of the workaround render target miptree
until update_renderbuffer time, so that we no longer need to skip
validation of miptrees used as render targets. As a bonus, this
should make GL_NV_texture_barrier possible.
(This also fixes a regression in the gen4 small-mipmap rendering since
3b38b33c1648b07e75dc4d8340758171e109c598, which switched
set_draw_offset from image->mt to irb->mt but didn't move the irb->mt
replacement up before set_draw_offset).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44961
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| bd3c10c0f0c60ab3421c2da2eab814edc2296cb0 |
|
16-Jan-2012 |
Brian Paul <brianp@vmware.com> |
swrast: s/Data/Map/ in swrast_texture_image
To indicate that it points to mapped texture memory.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| ab7794cada02f3b3b5e3a642c20eeedeb17b65a6 |
|
22-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Don't consider miptrees for other texture targets to match.
We would have done a relayout at validate time, but it's senseless to
store into a miptree if it's going to force relayout.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 7978fb4d9fd9c3e07aa1c09eba5571ec8a437d9c |
|
15-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Reuse intel_miptree_match_image().
This little bit of logic was duplicated, which isn't much, but I was
going to need to duplicate a bit of additional logic in the next
commit.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| d7b33309fe160212f2eb73f471f3aedcb5d0b5c1 |
|
15-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Kill intel_mipmap_level::nr_images [v4]
For all texture targets except GL_TEXTURE_CUBE_MAP, the 'nr_images' and
'depth' fields of intel_mipmap_level were identical. In the exceptional
case, nr_images == 6 and depth == 1.
It is simple to determine if a texture is a cube or not, so the presence
of two fields here was not helpful. Worse, it was confusing. When we
eventually implement GL_ARB_texture_cube_map_array, this mess would have
become even more confusing.
This patch removes 'nr_images' and assigns to 'depth' a consistent
meaning: depth is the number of 2D slices at each miplevel. The exact
semantics of depth varies according to the texture target:
- For GL_TEXTURE_CUBE_MAP, depth is 6.
- For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
identical for all miplevels in the texture.
- For GL_TEXTURE_3D, it is the texture's depth at each miplevel. Its
value, like width and height, varies with miplevel.
- For other texture types, depth is 1.
As a consequence, parameters were removed from the following function
signatures:
intel_miptree_set_level_info
Remove 'nr_images'.
i945_miptree_layout
brw_miptree_layout_texture
brw_miptree_layout_texture_array
Remove 'slices'.
v2:
- Replace "It's" with "Its".
- Remove all hunks in intel_fbo.c. The hunks were spurious and sneaked
in during a rebase.
- Remove unneeded hunk in intel_tex_map_image_for_swrast(). It was
a little refactor of the for-loop's upper bound.
v4:
In intel_miptree_get_image_offset(), document the conditions under
which different if-branches are taken.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 81d5195a6105606910d0d19ab059962e5712c2e0 |
|
01-Nov-2011 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
intel: fix potential segfault error
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 4ad8a0adec588b4c2c5a8f93265ed46cee5d3ff6 |
|
17-Oct-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop texture border support code.
Now that texture borders are gone, we never need to allocate our
textures through non-miptrees, which simplifies some irritating paths.
v2: Remove the !mt support case from intel_map_texture_image()
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 6e0f9001fe3fb191c2928bd09aa9e9d05ddf4ea9 |
|
23-Oct-2011 |
Brian Paul <brianp@vmware.com> |
mesa: move gl_texture_image::Data, RowStride, ImageOffsets to swrast
Only swrast and the drivers that fall back to swrast need these fields now.
This removes the last of the fields related to software rendering from
gl_texture_image.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| f8377b411dfe3c879eaab11bb86f509178796bd1 |
|
22-Sep-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Add 'mode' param to intel_region_map
The 'mode' param is a bitset of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT.
A future commit will perform buffer resolves in intel_region_map(). So,
even though the access mode is irrelevant to the GTT, the extra
information allows us to intelligently avoid unneccessary buffer resolves.
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 669f1822d2a60865514faf37f9fde21e4567b3d2 |
|
06-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_EXT_texture_array and GL_MESA_texture_array.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| fd99cd0e10849205749aad580fea8c970fb46a31 |
|
29-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add a helper function for getting miptree size from a texture image.
With 1D array textures, we no longer agree between the GL information
about width/height/depth of a texture and how we lay out a miptree.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| b07c78bfe94c17e6fccba70923b03a29c751fde1 |
|
29-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Consolidate texture validation copy code, and reuse it correctly.
The path for ->Data was failing to be called for the FBO draw offset
fallback, and also had mismatched compressed texture support code.
This drops the intel_prepare_render() in the blit path. We aren't
copying to/from a GL_FRONT buffer, so it doesn't matter.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 055995abc4e2f4a73122bd008a0e6f0558300d82 |
|
29-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Clean up the function chain for mapping texture images for swrast.
Too many separate functions each called from one location (in
different files). This code should all die soon when swrast starts
using MapTextureImage.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 32fe506ae14efa055f4773f422e2edd9fd1cffee |
|
22-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Allow src == NULL and *dst != NULL in intel_miptree_reference().
This makes this API consistent with intel_region_reference, and the
consumers wanted it this way.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| db3ada6055814a4bd5aa95fc9505fc101864391d |
|
22-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the "intel" argument to intel_miptree_release().
We don't have it in the other refcounting functions, and it was
totally unused.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| fa2c886863492cc3eeee6d2059ae24edc1cb2bff |
|
17-Sep-2011 |
Brian Paul <brianp@vmware.com> |
intel: make intel_texture_image a subclass of swrast_texture_image
We need to subclass swrast_texture_image because if we use swrast for
fallback rendering, we'll need to have swrast_texture_image objects.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 5b6264b42ec7e76565695b452801b775f820955e |
|
26-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Silence "warning: unused parameter ‘intel’"
The intel_context was not used in any of these functions, so remove it.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 7dae1aaf142999e3cfeafb13d30abda667d66d87 |
|
15-Jul-2011 |
Brian Paul <brianp@vmware.com> |
intel: use new gl_texture_image:Face, Level fields
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| f94fef83db10f0c9327bd3dd43510ad31c94d82a |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the cpp argument to intel_miptree_create().
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 6dcc398ac0837025cf60b4d6a056fa3b0a16466f |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Calculate compress_byte in intel_miptree_create.
One less argument and thing to get wrong.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 9c5fdbb721147f7304faaa8960f5b64e25a8f673 |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Use the gl_format to get the base_format for miptree create.
One less argument to this insanely long function call.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 9a523a48af05118424714f0a34ca3dda6861186a |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the internal_format field of the mipmap tree.
This has been replaced with the gl_format now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 0fac09a87c07d09dcd915c02b831505a53b02153 |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Make the intel_miptree_match_image format check more specific.
We don't care just about the internalFormat/cpp/compressed, but about
the specific format chosen. We have no support for format
translations as part of texture validation, and furthermore it has
restrictions in the GL specification. However, we should be making
consistent decisions for this check anyway.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| d5809115b568d8b74f47316607dce0730964517a |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add the MESA_FORMAT as a field of the miptree.
We only had internal_format before, which is way more irritating to
work with.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 1f32c665c8af0622e2bbf451edb999ffbcd7d0fe |
|
20-Apr-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add support for ARB_sampler_objects.
This extension support consists of replacing
"gl_texture_obj->Sampler." with "_mesa_get_samplerobj(ctx, unit)->".
One instance of referencing the texture's base sampler remains in the
initial miptree allocation, where I'm not sure we have a clear
association with any texture unit.
Tested with piglit ARB_sampler_objects/sampler-objects.
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| ecfaab88b2577bd0395bc05d75a036126806a9c4 |
|
10-Apr-2011 |
Brian Paul <brianp@vmware.com> |
mesa: move sampler state into new gl_sampler_object type
gl_texture_object contains an instance of this type for the regular
texture object sampling state. glGenSamplers() generates new instances
of gl_sampler_object which can override that state with glBindSampler().
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 6547253bd138db815173c00ca2dc220e8ad20ab1 |
|
04-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: check for miptree allocation failure
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 6bdc31942138f4dff5a701f26fe186a6e2e92275 |
|
10-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the speculatively-use-firstImage-mt in validation.
It's been replaced by just setting texObj->mt to image->mt at TexImage
time.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| bdc6dc1d7e7891ab00a2d08818093d5ecf249920 |
|
10-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Don't relayout the texture on maxlevel change.
This avoids relayouts in the common case of glGenerateMipmap() or
people doing similar things.
Bug #30366.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 5b3eb7538cd9ceb967b6e9e765896183e7c2c4d4 |
|
10-Jan-2011 |
Eric Anholt <eric@anholt.net> |
Revert "intel: Always allocate miptrees from level 0, not tObj->BaseLevel."
This reverts commit 7ce6517f3ac41bf770ab39aba4509d4f535ef663.
This reverts commit d60145d06d999c5c76000499e6fa9351e11d17fa.
I was wrong about which generations supported baselevel adjustment --
it's just gen4, nothing earlier. This meant that i915 would have
never used the mag filter when baselevel != 0. Not a severe bug, but
not an intentional regression. I think we can fix the performance
issue another way.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| a728646fb55245477d35e2761c3e0d15099b4cd4 |
|
06-Jan-2011 |
Zou Nan hai <nanhai.zou@intel.com> |
i965: skip too small size mipmap
this fixes doom3 crash.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 7ce6517f3ac41bf770ab39aba4509d4f535ef663 |
|
06-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Always allocate miptrees from level 0, not tObj->BaseLevel.
BaseLevel/MaxLevel are mostly used for two things: clamping texture
access for FBO rendering, and limiting the used mipmap levels when
incrementally loading textures. By restricting our mipmap trees to
just the current BaseLevel/MaxLevel, we caused reallocation thrashing
in the common case, for a theoretical win if someone really did want
just levels 2..4 or whatever of their texture object.
Bug #30366
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 1b18b45d79e065e4e05a1e89e9d756d96258ded5 |
|
06-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Clarify first_level/last_level vs baselevel/maxlevel by deletion.
This has always been ugly about our texture code -- object base/max
level vs intel object first/last level vs image level vs miptree
first/last level. We now get rid of intelObj->first_level which is
just tObj->BaseLevel, and make intelObj->_MaxLevel clearly based off
of tObj->_MaxLevel instead of duplicating its code (incorrectly, as
image->MaxLog2 only considers width/height and not depth!)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 973e821a633031fe5a8608b50beabb10af21430e |
|
05-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i915: Implement min/max lod clamping in hardware on 8xx.
This avoids 8xx-specific texture relayout for min/max lod changes.
One step closer to avoiding relayout for base/maxlevel changes!
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 6f31da584fd0c65095c325e60728f8230c66385a |
|
05-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop TEXTURE_RECTANGLE check in miptree layout setup.
It's already handled by our non-mipmapped MinFilter, since
TEXTURE_RECTANGLE is always NEAREST or LINEAR.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 8f0005bfd5dad4a338c23b9650baa3f5a1b0b06f |
|
05-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Clean up redundant setup of firstLevel.
It's always BaseLevel (since TEXTURE_RECTANGLE's baselevel can't be
changed from 0), except for 8xx minlod hilarity.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| e2ee0c55d360f6b0bb8cd140b6dd6c0f46998ab1 |
|
05-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop a check for GL_TEXTURE_4D_SGIS.
The SGIS_texture4D extension was thankfully never completed, so we
couldn't implement it if we wanted to.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| fb6bff3712d71cfe131fbf70154d326cdf39e7c8 |
|
23-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
intel: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 75bdbdd90b15c8704d87ca195a364ff6a42edbb1 |
|
04-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Don't validate in a texture image used as a render target.
Otherwise, we could lose track of rendering to that image, which could
easily happen during mipmap generation.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 8df81bca1704aef2f5cdc4052ef313d8f84f5d06 |
|
05-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Clean up some extra struct indirection in finalize.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| caf3038123d6d29afd7d1f0cd6db98a2282c3ca1 |
|
26-Oct-2009 |
Eric Anholt <eric@anholt.net> |
Make a convenient int for what chipset generation we're on.
gen2/3/4 are easier to say than "8xx, 915-945/g33/pineview, 965/g45/misc",
and compares on generation are often easier than stringing together a bunch
of chipset checks.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| f8f40b53a6a4551630e25bfd7f6e12334bb0f3f8 |
|
29-Oct-2009 |
Eric Anholt <eric@anholt.net> |
i915: Implement min/max LOD clamping with the hardware.
This gets us expected behavior for clamping between mipmap levels, and
avoids relayout of textures for doing clamping.
Fixes piglit lodclamp-between.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| b6bdafdf2cf1110b4a5ca7cf9e1c3dcb124b800f |
|
02-Oct-2009 |
Brian Paul <brianp@vmware.com> |
mesa: remove gl_texture_image::IsCompressed field
Use _mesa_is_format_compressed() instead.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 1f7c914ad0beea8a29c1a171c7cd1a12f2efe0fa |
|
01-Oct-2009 |
Brian Paul <brianp@vmware.com> |
mesa: replace gl_texture_format with gl_format
Now gl_texture_image::TexFormat is a simple MESA_FORMAT_x enum.
ctx->Driver.ChooseTexture format also returns a MESA_FORMAT_x.
gl_texture_format will go away next.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 9fbb8884f034e0d691fed0e099d4d796f3b42848 |
|
28-Sep-2009 |
Brian Paul <brianp@vmware.com> |
mesa/drivers: use _mesa_get_format_bytes()
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 9c0ba017c8ff7caafc3ff94da3c035e687231596 |
|
23-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix depth-texture Y-tiling detection for sized internal formats.
Fixes assertion failure on norsetto shadow mapping demo.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 467f18f7a5375af9a31031063536c927df3ea70c |
|
20-May-2009 |
Eric Anholt <eric@anholt.net> |
intel: Don't segfault on glGenerateMipmaps of a cube map with one face defined.
This presumably applies to SGIS_generate_mipmaps as well.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 40dd024be618d805b3744e15d25e115018641324 |
|
18-Feb-2009 |
Eric Anholt <eric@anholt.net> |
intel: tell libdrm whether we want a cpu-ready or gpu-ready BO for regions.
This lets us avoid allocing new buffers for renderbuffers, finalized miptrees,
and PBO-uploaded textures when there's an unreferenced but still active one
cached, while also avoiding CPU waits for batchbuffers and CPU-uploaded
textures. The size of BOs allocated for a desktop running current GL
cairogears on i915 is cut in half with this.
Note that this means we require libdrm 2.4.5.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 9aec1288eeae8e87adc9a99f377be536892941b2 |
|
09-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i915: Accelerate depth textures with border color.
The fallback was introduced to fix bug #16697, but made the test it was
fixing run excessively long.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 495c02262eaaa68f2df23c2265362da51851c57a |
|
21-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel: Fix SGIS_generate_mipmap after a miptree had been validated.
Previously, the updated images would be ignored because the miptree in the
image matched the miptree in the object, even though Mesa core had just attached
updated contents in ->Data. Additionally, Mesa core could have tried to
free inside our miptree if it had already been validated.
Fixes bug #17077.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 1e645b365900cf1c71ca5594bd6b549a1f203040 |
|
26-Jul-2008 |
Ian Romanick <ian.d.romanick@intel.com> |
Merge branch 'master' into drm-gem
Conflicts:
src/mesa/drivers/dri/common/dri_bufmgr.c
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b4b7326717d3253656f9702fc04f06f8d210a6aa |
|
18-Jul-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
intel: fix texture border issue. (bug #16697)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| bcc2a3d7e3c5f81bb5a45b8d628a133f3b5499a5 |
|
01-Jul-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
dri: Take the base image size into account when computing
first level of the mipmap. fix #16210
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 93f701bc3619864ac6f067d37212e96545a57e16 |
|
26-Jun-2008 |
Eric Anholt <eric@anholt.net> |
intel: Replace sprinkled intel_batchbuffer_flush with MI_FLUSH or nothing.
Most of these were to ensure that caches got synchronized between 2d (or meta)
rendering and later use of the target as a source, such as for texture
miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(),
which just drops an MI_FLUSH. Most of the remainder were to ensure that
REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped.
Those are now replaced by automatically flushing those when dropping the lock.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 101abee6c4fc2c9284ff2ba6f9f9138327d6963d |
|
19-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Fix and reenable (software) SGIS_generate_mipmap
The core problem was that _mesa_generate_mipmap was not respecting RowStride
of the source image. Additionally, the intel private data associated with the
images (level and face) was not being initialized for the
_mesa_generate_mipmap-generated images.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| c0b4257aa9ba783674ccf7162799385734dff211 |
|
16-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Move to using shared texture management code.
This removes the delayed texture upload optimization from 965, in exchange for
bringing us closer to PBO support. It also disables SGIS_generate_mipmap,
which didn't seem to be working before anyway, according to the lodbias demo.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|
| 77a5bcaff43df8d54e0e0ef833726e4b41d7eb36 |
|
07-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Move over files that will be shared with 965-fbo work.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_validate.c
|