/drivers/gpu/drm/exynos/ |
H A D | exynos_dp_reg.c | 32 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 34 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 36 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 38 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 46 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 48 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 62 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); 70 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1); 73 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2); 76 writel(reg, dp->reg_base [all...] |
/drivers/video/fbdev/exynos/ |
H A D | exynos_mipi_dsi_lowlevel.c | 36 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); 40 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); 47 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); 51 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); 58 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); 62 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); 67 return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) & 75 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK); 90 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK); 98 reg = readl(dsim->reg_base [all...] |
/drivers/gpio/ |
H A D | gpio-bcm-kona.c | 65 void __iomem *reg_base; member in struct:bcm_kona_gpio 86 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base, argument 89 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); 90 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); 102 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); 104 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); 118 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); 120 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); 128 void __iomem *reg_base; local 135 reg_base 159 void __iomem *reg_base; local 202 void __iomem *reg_base; local 224 void __iomem *reg_base; local 263 void __iomem *reg_base; local 325 void __iomem *reg_base; local 346 void __iomem *reg_base; local 367 void __iomem *reg_base; local 388 void __iomem *reg_base; local 432 void __iomem *reg_base; local 545 void __iomem *reg_base; local [all...] |
/drivers/video/fbdev/mmp/hw/ |
H A D | mmp_spi.c | 47 void *reg_base = local 51 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); 55 writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA); 58 writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA); 61 writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA); 68 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); 71 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); 73 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); 76 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); 84 tmp = readl_relaxed(reg_base 96 void *reg_base = local [all...] |
/drivers/ide/ |
H A D | opti621.c | 29 static int reg_base; variable 34 * is at reg_base (0x1f0 primary, 0x170 secondary, 40 inw(reg_base + 1); 41 inw(reg_base + 1); 42 outb(3, reg_base + 2); 43 outb(value, reg_base + reg); 44 outb(0x83, reg_base + 2); 48 * is at reg_base (0x1f0 primary, 0x170 secondary, 56 inw(reg_base + 1); 57 inw(reg_base [all...] |
/drivers/irqchip/ |
H A D | irq-atmel-aic.c | 68 irqnr = irq_reg_readl(gc->reg_base + AT91_AIC_IVR); 69 irqstat = irq_reg_readl(gc->reg_base + AT91_AIC_ISR); 72 irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR); 83 irq_reg_writel(d->mask, gc->reg_base + AT91_AIC_ISCR); 95 smr = irq_reg_readl(gc->reg_base + AT91_AIC_SMR(d->hwirq)); 100 irq_reg_writel(smr, gc->reg_base + AT91_AIC_SMR(d->hwirq)); 111 irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IDCR); 112 irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IECR); 121 irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IDCR); 122 irq_reg_writel(gc->mask_cache, gc->reg_base [all...] |
H A D | irq-atmel-aic5.c | 78 irqnr = irq_reg_readl(gc->reg_base + AT91_AIC5_IVR); 79 irqstat = irq_reg_readl(gc->reg_base + AT91_AIC5_ISR); 82 irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR); 95 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 96 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR); 109 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 110 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IECR); 123 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 124 irq_reg_writel(1, gc->reg_base + AT91_AIC5_ISCR); 139 irq_reg_writel(d->hwirq, gc->reg_base [all...] |
/drivers/clk/rockchip/ |
H A D | softrst.c | 24 void __iomem *reg_base; member in struct:rockchip_softrst 42 softrst->reg_base + (bank * 4)); 49 reg = readl(softrst->reg_base + (bank * 4)); 50 writel(reg | BIT(offset), softrst->reg_base + (bank * 4)); 68 writel((BIT(offset) << 16), softrst->reg_base + (bank * 4)); 75 reg = readl(softrst->reg_base + (bank * 4)); 76 writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4)); 102 softrst->reg_base = base;
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H A D | clk-pll.c | 38 void __iomem *reg_base; member in struct:rockchip_clk_pll 136 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); 143 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); 146 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); 198 pll->reg_base + RK3066_PLLCON(3)); 205 pll->reg_base + RK3066_PLLCON(0)); 209 pll->reg_base + RK3066_PLLCON(1)); 212 pll->reg_base + RK3066_PLLCON(2)); 216 pll->reg_base + RK3066_PLLCON(3)); 238 pll->reg_base [all...] |
H A D | clk-cpu.c | 46 * @reg_base: base register for cpu-clock values. 61 void __iomem *reg_base; member in struct:rockchip_cpuclk 93 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg); 118 writel(clksel->val , cpuclk->reg_base + clksel->reg); 160 cpuclk->reg_base + reg_data->core_reg); 164 cpuclk->reg_base + reg_data->core_reg); 199 cpuclk->reg_base + reg_data->core_reg); 235 int nrates, void __iomem *reg_base, spinlock_t *lock) 264 cpuclk->reg_base = reg_base; 231 rockchip_clk_register_cpuclk(const char *name, const char **parent_names, u8 num_parents, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, int nrates, void __iomem *reg_base, spinlock_t *lock) argument [all...] |
/drivers/clk/samsung/ |
H A D | clk-exynos-audss.c | 30 static void __iomem *reg_base; variable 49 reg_save[i][1] = readl(reg_base + reg_save[i][0]); 59 writel(reg_save[i][1], reg_base + reg_save[i][0]); 96 reg_base = devm_ioremap_resource(&pdev->dev, res); 97 if (IS_ERR(reg_base)) { 99 return PTR_ERR(reg_base); 123 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); 134 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); 137 "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4, 142 reg_base [all...] |
H A D | clk-s5pv210-audss.c | 28 static void __iomem *reg_base; variable 47 reg_save[i][1] = readl(reg_base + reg_save[i][0]); 57 writel(reg_save[i][1], reg_base + reg_save[i][0]); 77 reg_base = devm_ioremap_resource(&pdev->dev, res); 78 if (IS_ERR(reg_base)) { 80 return PTR_ERR(reg_base); 122 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); 133 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); 137 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); 139 "mout_i2s_audss", 0, reg_base [all...] |
H A D | clk-exynos5440.c | 95 void __iomem *reg_base; local 98 reg_base = of_iomap(np, 0); 99 if (!reg_base) { 105 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 112 samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10); 113 samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
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H A D | clk-s3c2412.c | 37 static void __iomem *reg_base; variable 57 samsung_clk_save(reg_base, s3c2412_save, 65 samsung_clk_restore(reg_base, s3c2412_save, 221 __raw_writel(0x00, reg_base + CLKSRC); 222 __raw_writel(0x533C2412, reg_base + SWRST); 261 reg_base = base; 264 reg_base = of_iomap(np, 0); 265 if (!reg_base) 269 ctx = samsung_clk_init(np, reg_base, NR_CLKS); 279 reg_base); [all...] |
/drivers/spi/ |
H A D | spi-fsl-espi.c | 92 struct fsl_espi_reg *reg_base = mspi->reg_base; local 93 __be32 __iomem *mode = ®_base->csmode[spi->chip_select]; 94 __be32 __iomem *espi_mode = ®_base->mode; 203 struct fsl_espi_reg *reg_base = mspi->reg_base; local 208 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); 212 mpc8xxx_spi_write_reg(®_base->transmit, word); 220 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; local 451 struct fsl_espi_reg *reg_base; local 509 struct fsl_espi_reg *reg_base = mspi->reg_base; local 569 struct fsl_espi_reg *reg_base = mspi->reg_base; local 596 struct fsl_espi_reg *reg_base; local 766 struct fsl_espi_reg *reg_base; local 791 struct fsl_espi_reg *reg_base; local [all...] |
H A D | spi-fsl-spi.c | 90 struct fsl_spi_reg *reg_base = mspi->reg_base; local 91 __be32 __iomem *mode = ®_base->mode; 292 struct fsl_spi_reg *reg_base = mspi->reg_base; local 297 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); 301 mpc8xxx_spi_write_reg(®_base->transmit, word); 310 struct fsl_spi_reg *reg_base; local 315 reg_base = mpc8xxx_spi->reg_base; 425 struct fsl_spi_reg *reg_base; local 510 struct fsl_spi_reg *reg_base = mspi->reg_base; local 545 struct fsl_spi_reg *reg_base = mspi->reg_base; local 571 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; local 589 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; local 615 struct fsl_spi_reg *reg_base; local [all...] |
/drivers/ata/ |
H A D | ahci_sunxi.c | 86 static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) argument 92 writel(0, reg_base + AHCI_RWCR); 95 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); 96 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, 99 sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, 102 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); 103 sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); 104 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, 106 sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, 110 sunxi_setbits(reg_base [all...] |
/drivers/clk/mvebu/ |
H A D | clk-cpu.c | 39 void __iomem *reg_base; member in struct:cpu_clk 55 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); 84 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) 87 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); 91 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) 93 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); 96 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) 98 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); 103 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); 125 reg = readl(cpuclk->reg_base [all...] |
/drivers/input/keyboard/ |
H A D | nspire-keypad.c | 35 void __iomem *reg_base; member in struct:nspire_keypad 64 int_sts = readl(keypad->reg_base + KEYPAD_INT) & keypad->int_mask; 68 memcpy_fromio(state, keypad->reg_base + KEYPAD_DATA, sizeof(state)); 94 writel(0x3, keypad->reg_base + KEYPAD_INT); 118 writel(val, keypad->reg_base + KEYPAD_SCAN_MODE); 121 writel(val, keypad->reg_base + KEYPAD_CNTL); 125 writel(keypad->int_mask, keypad->reg_base + KEYPAD_INTMSK); 129 writel(0, keypad->reg_base + KEYPAD_UNKNOWN_INT); 131 writel(~0, keypad->reg_base + KEYPAD_UNKNOWN_INT_STS); 208 keypad->reg_base [all...] |
/drivers/ntb/ |
H A D | ntb_hw.c | 547 writeb(0xe0, ndev->reg_base + BWD_MODPHY_PCSREG6); 548 writeb(0x40, ndev->reg_base + BWD_MODPHY_PCSREG4); 549 writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG4); 550 writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG6); 556 status = readl(ndev->reg_base + BWD_ERRCORSTS_OFFSET); 559 writel(status, ndev->reg_base + BWD_ERRCORSTS_OFFSET); 562 status = readl(ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET); 565 writel(status, ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET); 568 status = readl(ndev->reg_base + BWD_DESKEWSTS_OFFSET); 571 writel(status, ndev->reg_base [all...] |
/drivers/usb/host/ |
H A D | ohci-octeon.c | 109 void *reg_base; local 141 reg_base = devm_ioremap_resource(&pdev->dev, res_mem); 142 if (IS_ERR(reg_base)) { 143 ret = PTR_ERR(reg_base); 149 hcd->regs = reg_base;
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/drivers/i2c/busses/ |
H A D | i2c-pca-platform.c | 30 void __iomem *reg_base; member in struct:i2c_pca_pf_data 45 return ioread8(i2c->reg_base + reg); 51 return ioread8(i2c->reg_base + reg * 2); 57 return ioread8(i2c->reg_base + reg * 4); 63 iowrite8(val, i2c->reg_base + reg); 69 iowrite8(val, i2c->reg_base + reg * 2); 75 iowrite8(val, i2c->reg_base + reg * 4); 164 i2c->reg_base = ioremap(res->start, resource_size(res)); 165 if (!i2c->reg_base) { 249 iounmap(i2c->reg_base); [all...] |
H A D | i2c-mv64xxx.c | 130 void __iomem *reg_base; member in struct:mv64xxx_i2c_data 232 drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO); 234 drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI); 242 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); 253 u32 data_reg_lo = readl(drv_data->reg_base + 255 u32 data_reg_hi = readl(drv_data->reg_base + 278 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); 279 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING); 280 writel(0, drv_data->reg_base + 282 writel(0, drv_data->reg_base [all...] |
/drivers/dma/ioat/ |
H A D | dma.h | 44 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80) 62 * @reg_base: MMIO register space base address 80 void __iomem *reg_base; member in struct:ioatdma_device 102 void __iomem *reg_base; member in struct:ioat_chan_common 232 status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); 233 status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); 249 status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver)); 264 writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 274 return readl(chan->reg_base [all...] |
/drivers/clocksource/ |
H A D | exynos_mct.c | 80 static void __iomem *reg_base; variable 97 writel_relaxed(value, reg_base + offset); 147 if (readl_relaxed(reg_base + stat_addr) & mask) { 148 writel_relaxed(mask, reg_base + stat_addr); 160 reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); 178 u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); 182 lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); 183 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); 199 return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); 253 tcon = readl_relaxed(reg_base [all...] |