/drivers/clk/keystone/ |
H A D | Makefile | 1 obj-y += pll.o gate.o
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/drivers/clk/zynq/ |
H A D | Makefile | 3 obj-$(CONFIG_ARCH_ZYNQ) += clkc.o pll.o
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H A D | pll.c | 200 struct zynq_pll *pll; local 213 pll = kmalloc(sizeof(*pll), GFP_KERNEL); 214 if (!pll) 218 pll->hw.init = &initd; 219 pll->pll_ctrl = pll_ctrl; 220 pll->pll_status = pll_status; 221 pll->lockbit = lock_index; 222 pll->lock = lock; 224 spin_lock_irqsave(pll [all...] |
/drivers/media/i2c/ |
H A D | aptina-pll.c | 27 #include "aptina-pll.h" 31 struct aptina_pll *pll) 41 pll->ext_clock, pll->pix_clock); 43 if (pll->ext_clock < limits->ext_clock_min || 44 pll->ext_clock > limits->ext_clock_max) { 45 dev_err(dev, "pll: invalid external clock frequency.\n"); 49 if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) { 50 dev_err(dev, "pll 29 aptina_pll_calculate(struct device *dev, const struct aptina_pll_limits *limits, struct aptina_pll *pll) argument [all...] |
H A D | smiapp-pll.c | 2 * drivers/media/i2c/smiapp-pll.c 29 #include "smiapp-pll.h" 66 static void print_pll(struct device *dev, struct smiapp_pll *pll) argument 68 dev_dbg(dev, "pre_pll_clk_div\t%d\n", pll->pre_pll_clk_div); 69 dev_dbg(dev, "pll_multiplier \t%d\n", pll->pll_multiplier); 70 if (pll->flags != SMIAPP_PLL_FLAG_NO_OP_CLOCKS) { 71 dev_dbg(dev, "op_sys_clk_div \t%d\n", pll->op_sys_clk_div); 72 dev_dbg(dev, "op_pix_clk_div \t%d\n", pll->op_pix_clk_div); 74 dev_dbg(dev, "vt_sys_clk_div \t%d\n", pll->vt_sys_clk_div); 75 dev_dbg(dev, "vt_pix_clk_div \t%d\n", pll 101 __smiapp_pll_calculate(struct device *dev, const struct smiapp_pll_limits *limits, struct smiapp_pll *pll, uint32_t mul, uint32_t div, uint32_t lane_op_clock_ratio) argument 378 smiapp_pll_calculate(struct device *dev, const struct smiapp_pll_limits *limits, struct smiapp_pll *pll) argument [all...] |
H A D | aptina-pll.h | 54 struct aptina_pll *pll);
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/drivers/clk/mxs/ |
H A D | clk-pll.c | 21 * struct clk_pll - mxs pll clock 22 * @hw: clk_hw for the pll 23 * @base: base address of the pll 25 * @rate: the clock rate of the pll 27 * The mxs pll is a fixed rate clock with power and gate control, 41 struct clk_pll *pll = to_clk_pll(hw); local 43 writel_relaxed(1 << pll->power, pll->base + SET); 52 struct clk_pll *pll = to_clk_pll(hw); local 54 writel_relaxed(1 << pll 59 struct clk_pll *pll = to_clk_pll(hw); local 68 struct clk_pll *pll = to_clk_pll(hw); local 76 struct clk_pll *pll = to_clk_pll(hw); local 92 struct clk_pll *pll; local [all...] |
/drivers/video/fbdev/aty/ |
H A D | mach64_ct.c | 17 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll); 18 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll); 19 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll); 20 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll); 119 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) argument 126 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; 127 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; 129 ras_multiplier = pll 208 aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll) argument 250 aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) argument 263 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll) argument 280 aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll) argument 376 aty_get_pll_ct(const struct fb_info *info, union aty_pll *pll) argument 399 aty_init_pll_ct(const struct fb_info *info, union aty_pll *pll) argument 604 aty_resume_pll_ct(const struct fb_info *info, union aty_pll *pll) argument [all...] |
/drivers/clk/tegra/ |
H A D | clk-pll.c | 223 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) argument 227 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) 230 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) 233 val = pll_readl_misc(pll); 234 val |= BIT(pll->params->lock_enable_bit_idx); 235 pll_writel_misc(val, pll); 238 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) argument 244 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { 245 udelay(pll->params->lock_delay); 249 lock_addr = pll 274 struct tegra_clk_pll *pll = to_clk_pll(hw); local 290 struct tegra_clk_pll *pll = to_clk_pll(hw); local 310 struct tegra_clk_pll *pll = to_clk_pll(hw); local 328 struct tegra_clk_pll *pll = to_clk_pll(hw); local 347 struct tegra_clk_pll *pll = to_clk_pll(hw); local 361 struct tegra_clk_pll *pll = to_clk_pll(hw); local 377 struct tegra_clk_pll *pll = to_clk_pll(hw); local 396 struct tegra_clk_pll *pll = to_clk_pll(hw); local 420 struct tegra_clk_pll *pll = to_clk_pll(hw); local 479 _update_pll_mnp(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg) argument 514 _get_pll_mnp(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg) argument 539 _update_pll_cpcon(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg, unsigned long rate) argument 566 struct tegra_clk_pll *pll = to_clk_pll(hw); local 590 struct tegra_clk_pll *pll = to_clk_pll(hw); local 629 struct tegra_clk_pll *pll = to_clk_pll(hw); local 649 struct tegra_clk_pll *pll = to_clk_pll(hw); local 688 clk_plle_training(struct tegra_clk_pll *pll) argument 731 struct tegra_clk_pll *pll = to_clk_pll(hw); local 788 struct tegra_clk_pll *pll = to_clk_pll(hw); local 874 struct tegra_clk_pll *pll = to_clk_pll(hw); local 900 struct tegra_clk_pll *pll = to_clk_pll(hw); local 922 struct tegra_clk_pll *pll = to_clk_pll(hw); local 950 struct tegra_clk_pll *pll = to_clk_pll(hw); local 979 struct tegra_clk_pll *pll = to_clk_pll(hw); local 1027 struct tegra_clk_pll *pll = to_clk_pll(hw); local 1057 _pllcx_strobe(struct tegra_clk_pll *pll) argument 1072 struct tegra_clk_pll *pll = to_clk_pll(hw); local 1100 struct tegra_clk_pll *pll = to_clk_pll(hw); local 1113 struct tegra_clk_pll *pll = to_clk_pll(hw); local 1125 _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, unsigned long input_rate, u32 n) argument 1163 struct tegra_clk_pll *pll = to_clk_pll(hw); local 1204 _pllre_calc_rate(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) argument 1228 struct tegra_clk_pll *pll = to_clk_pll(hw); local 1262 struct tegra_clk_pll *pll = to_clk_pll(hw); local 1276 struct tegra_clk_pll *pll = to_clk_pll(hw); local 1283 struct tegra_clk_pll *pll = to_clk_pll(hw); local 1392 struct tegra_clk_pll *pll = to_clk_pll(hw); local 1415 struct tegra_clk_pll *pll; local 1433 _tegra_clk_register_pll(struct tegra_clk_pll *pll, const char *name, const char *parent_name, unsigned long flags, const struct clk_ops *ops) argument 1456 struct tegra_clk_pll *pll; local 1487 struct tegra_clk_pll *pll; local 1559 struct tegra_clk_pll *pll; local 1613 struct tegra_clk_pll *pll; local 1658 struct tegra_clk_pll *pll; local 1699 struct tegra_clk_pll *pll; local 1771 struct tegra_clk_pll *pll; local 1820 struct tegra_clk_pll *pll; local [all...] |
/drivers/video/fbdev/matrox/ |
H A D | g450_pll.h | 7 unsigned int pll); 10 unsigned int pll);
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H A D | matroxfb_misc.h | 7 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax, 14 return matroxfb_PLL_calcclock(&minfo->features.pll, freq, fmax, in, feed, post);
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H A D | g450_pll.c | 35 return (minfo->features.pll.ref_freq * n + (m >> 1)) / m; 99 n = ((tvco * (m+1) + minfo->features.pll.ref_freq) / (minfo->features.pll.ref_freq * 2)) - 2; 137 unsigned int mnp, unsigned int pll) 139 switch (pll) { 174 unsigned int mnp, unsigned int pll) 180 switch (pll) { 230 unsigned int pll) 232 return g450_isplllocked(minfo, g450_setpll(minfo, mnp, pll)); 235 static void updatehwstate_clk(struct matrox_hw_state* hw, unsigned int mnp, unsigned int pll) { argument 136 g450_setpll(const struct matrox_fb_info *minfo, unsigned int mnp, unsigned int pll) argument 173 g450_cmppll(const struct matrox_fb_info *minfo, unsigned int mnp, unsigned int pll) argument 229 g450_testpll(const struct matrox_fb_info *minfo, unsigned int mnp, unsigned int pll) argument 245 matroxfb_g450_setpll_cond(struct matrox_fb_info *minfo, unsigned int mnp, unsigned int pll) argument 253 g450_findworkingpll(struct matrox_fb_info *minfo, unsigned int pll, unsigned int *mnparray, unsigned int mnpcount) argument 331 __g450_setclk(struct matrox_fb_info *minfo, unsigned int fout, unsigned int pll, unsigned int *mnparray, unsigned int *deltaarray) argument 516 matroxfb_g450_setclk(struct matrox_fb_info *minfo, unsigned int fout, unsigned int pll) argument [all...] |
/drivers/clk/qcom/ |
H A D | clk-pll.c | 25 #include "clk-pll.h" 39 struct clk_pll *pll = to_clk_pll(hw); local 44 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); 53 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, 65 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, 74 ret = regmap_update_bits(pll->clkr.regmap, pll 84 struct clk_pll *pll = to_clk_pll(hw); local 99 struct clk_pll *pll = to_clk_pll(hw); local 146 struct clk_pll *pll = to_clk_pll(hw); local 159 struct clk_pll *pll = to_clk_pll(hw); local 195 wait_for_pll(struct clk_pll *pll) argument 235 clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap, u8 lock_count) argument 254 clk_pll_configure(struct clk_pll *pll, struct regmap *regmap, const struct pll_config *config) argument 281 clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, const struct pll_config *config, bool fsm_mode) argument 290 clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, const struct pll_config *config, bool fsm_mode) argument [all...] |
/drivers/clk/rockchip/ |
H A D | clk-pll.c | 52 struct rockchip_clk_pll *pll, unsigned long rate) 54 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; 57 for (i = 0; i < pll->rate_count; i++) { 68 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); local 69 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; 73 for (i = 0; i < pll->rate_count; i++) { 83 * Wait for the pll to reach the locked state. 87 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) argument 94 ret = regmap_read(grf, pll->lock_offset, &val); 96 pr_err("%s: failed to read pll loc 51 rockchip_get_pll_settings( struct rockchip_clk_pll *pll, unsigned long rate) argument 132 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); local 160 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); local 235 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); local 245 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); local 254 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); local 289 struct rockchip_clk_pll *pll; local [all...] |
/drivers/clk/st/ |
H A D | clkgen.h | 41 #define CLKGEN_READ(pll, field) clkgen_read(pll->regs_base, \ 42 &pll->data->field) 44 #define CLKGEN_WRITE(pll, field, val) clkgen_write(pll->regs_base, \ 45 &pll->data->field, val)
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H A D | Makefile | 1 obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o clk-flexgen.o
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/drivers/video/fbdev/via/ |
H A D | via_clock.h | 63 struct via_pll_config pll) 65 return ref_freq / pll.divisor * pll.multiplier; 69 struct via_pll_config pll) 71 return get_pll_internal_frequency(ref_freq, pll) >> pll.rshift; 62 get_pll_internal_frequency(u32 ref_freq, struct via_pll_config pll) argument 68 get_pll_output_frequency(u32 ref_freq, struct via_pll_config pll) argument
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/drivers/clk/at91/ |
H A D | clk-pll.c | 74 struct clk_pll *pll = (struct clk_pll *)dev_id; local 76 wake_up(&pll->wait); 77 disable_irq_nosync(pll->irq); 84 struct clk_pll *pll = to_clk_pll(hw); local 85 struct at91_pmc *pmc = pll->pmc; 86 const struct clk_pll_layout *layout = pll->layout; 88 pll->characteristics; 89 u8 id = pll->id; 102 (div == pll->div && mul == pll 132 struct clk_pll *pll = to_clk_pll(hw); local 141 struct clk_pll *pll = to_clk_pll(hw); local 153 struct clk_pll *pll = to_clk_pll(hw); local 161 clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate, unsigned long parent_rate, u32 *div, u32 *mul, u32 *index) argument 266 struct clk_pll *pll = to_clk_pll(hw); local 275 struct clk_pll *pll = to_clk_pll(hw); local 308 struct clk_pll *pll; local [all...] |
/drivers/video/fbdev/omap2/dss/ |
H A D | hdmi_pll.c | 38 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) argument 41 hdmi_read_reg(pll->base, r)) 54 void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy) argument 56 struct hdmi_pll_info *pi = &pll->info; 107 static int hdmi_pll_config(struct hdmi_pll_data *pll) argument 110 struct hdmi_pll_info *fmt = &pll->info; 113 REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); 115 r = hdmi_read_reg(pll->base, PLLCTRL_CFG1); 118 hdmi_write_reg(pll->base, PLLCTRL_CFG1, r); 120 r = hdmi_read_reg(pll 169 hdmi_pll_reset(struct hdmi_pll_data *pll) argument 184 hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp) argument 207 hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp) argument 268 hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll) argument [all...] |
/drivers/clk/berlin/ |
H A D | berlin2-pll.c | 56 * The output frequency formula for the pll is: 62 struct berlin2_pll *pll = to_berlin2_pll(hw); local 63 struct berlin2_pll_map *map = &pll->map; 67 val = readl_relaxed(pll->base + SPLL_CTRL0); 75 val = readl_relaxed(pll->base + SPLL_CTRL1); 100 struct berlin2_pll *pll; local 102 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 103 if (!pll) 107 memcpy(&pll [all...] |
H A D | Makefile | 1 obj-y += berlin2-avpll.o berlin2-pll.o berlin2-div.o
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/drivers/clk/samsung/ |
H A D | clk-pll.c | 9 * This file contains the utility functions to register the pll clocks. 16 #include "clk-pll.h" 32 struct samsung_clk_pll *pll, unsigned long rate) 34 const struct samsung_pll_rate_table *rate_table = pll->rate_table; 37 for (i = 0; i < pll->rate_count; i++) { 48 struct samsung_clk_pll *pll = to_clk_pll(hw); local 49 const struct samsung_pll_rate_table *rate_table = pll->rate_table; 53 for (i = 0; i < pll->rate_count; i++) { 76 struct samsung_clk_pll *pll = to_clk_pll(hw); local 80 pll_con = __raw_readl(pll 31 samsung_get_pll_settings( struct samsung_clk_pll *pll, unsigned long rate) argument 109 struct samsung_clk_pll *pll = to_clk_pll(hw); local 146 struct samsung_clk_pll *pll = to_clk_pll(hw); local 175 struct samsung_clk_pll *pll = to_clk_pll(hw); local 249 struct samsung_clk_pll *pll = to_clk_pll(hw); local 284 struct samsung_clk_pll *pll = to_clk_pll(hw); local 363 struct samsung_clk_pll *pll = to_clk_pll(hw); local 397 struct samsung_clk_pll *pll = to_clk_pll(hw); local 508 struct samsung_clk_pll *pll = to_clk_pll(hw); local 544 struct samsung_clk_pll *pll = to_clk_pll(hw); local 642 struct samsung_clk_pll *pll = to_clk_pll(hw); local 682 struct samsung_clk_pll *pll = to_clk_pll(hw); local 720 struct samsung_clk_pll *pll = to_clk_pll(hw); local 738 struct samsung_clk_pll *pll = to_clk_pll(hw); local 756 struct samsung_clk_pll *pll = to_clk_pll(hw); local 787 struct samsung_clk_pll *pll = to_clk_pll(hw); local 891 struct samsung_clk_pll2550x *pll = to_clk_pll2550x(hw); local 917 struct samsung_clk_pll2550x *pll; local 969 struct samsung_clk_pll *pll = to_clk_pll(hw); local 997 struct samsung_clk_pll *pll = to_clk_pll(hw); local 1074 struct samsung_clk_pll *pll = to_clk_pll(hw); local 1096 struct samsung_clk_pll *pll = to_clk_pll(hw); local 1151 struct samsung_clk_pll *pll; local [all...] |
/drivers/clk/socfpga/ |
H A D | Makefile | 3 obj-y += clk-pll.o
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/drivers/clk/spear/ |
H A D | clk-vco-pll.c | 12 #define pr_fmt(fmt) "clk-vco-pll: " fmt 31 * pll_rate = pll/2^p 33 * vco and pll are very closely bound to each other, "vco needs to program: 34 * mode, m & n" and "pll needs to program p", both share common enable/disable 37 * clk_register_vco_pll() registers instances of both vco & pll. 38 * CLK_SET_RATE_PARENT flag is forced for pll, as it will always pass its 68 /* Calculates pll clk rate for specific value of mode, m, n and p */ 87 struct clk_pll *pll = to_clk_pll(hw); local 93 pr_err("%s: prate is must for pll clk\n", __func__); 97 for (*index = 0; *index < pll 127 struct clk_pll *pll = to_clk_pll(hw); local 147 struct clk_pll *pll = to_clk_pll(hw); local 283 struct clk_pll *pll; local [all...] |
/drivers/gpu/drm/nouveau/core/subdev/clock/ |
H A D | nva3.h | 8 u32 pll; member in struct:nva3_clock_info
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