Searched refs:base (Results 1 - 25 of 1118) sorted by relevance

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/drivers/pci/
H A Dmsi.h9 #define msi_control_reg(base) (base + PCI_MSI_FLAGS)
10 #define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
11 #define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
12 #define msi_data_reg(base, is64bit) \
13 (base + ((is64bit == 1) ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32))
14 #define msi_mask_reg(base, is64bit) \
15 (base
[all...]
/drivers/watchdog/
H A Dnv_tco.h34 #define TCO_RLD(base) ((base) + 0x00) /* TCO Timer Reload and Current Value */
35 #define TCO_TMR(base) ((base) + 0x01) /* TCO Timer Initial Value */
37 #define TCO_STS(base) ((base) + 0x04) /* TCO Status Register */
53 #define TCO_CNT(base) ((base) + 0x08) /* TCO Control Register */
60 * The SMI_EN register is at the base io address + 0x04,
63 #define MCP51_SMI_EN(base) ((bas
[all...]
H A Dsp5100_tco.h14 #define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */
15 #define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */
/drivers/scsi/
H A Dnsp32_io.h12 static inline void nsp32_write1(unsigned int base, argument
16 outb(val, (base + index));
19 static inline unsigned char nsp32_read1(unsigned int base, argument
22 return inb(base + index);
25 static inline void nsp32_write2(unsigned int base, argument
29 outw(val, (base + index));
32 static inline unsigned short nsp32_read2(unsigned int base, argument
35 return inw(base + index);
38 static inline void nsp32_write4(unsigned int base, argument
42 outl(val, (base
45 nsp32_read4(unsigned int base, unsigned int index) argument
53 nsp32_mmio_write1(unsigned long base, unsigned int index, unsigned char val) argument
64 nsp32_mmio_read1(unsigned long base, unsigned int index) argument
74 nsp32_mmio_write2(unsigned long base, unsigned int index, unsigned short val) argument
85 nsp32_mmio_read2(unsigned long base, unsigned int index) argument
95 nsp32_mmio_write4(unsigned long base, unsigned int index, unsigned long val) argument
106 nsp32_mmio_read4(unsigned long base, unsigned int index) argument
118 nsp32_index_read1(unsigned int base, unsigned int reg) argument
125 nsp32_index_write1(unsigned int base, unsigned int reg, unsigned char val) argument
133 nsp32_index_read2(unsigned int base, unsigned int reg) argument
140 nsp32_index_write2(unsigned int base, unsigned int reg, unsigned short val) argument
148 nsp32_index_read4(unsigned int base, unsigned int reg) argument
160 nsp32_index_write4(unsigned int base, unsigned int reg, unsigned long val) argument
176 nsp32_mmio_index_read1(unsigned long base, unsigned int reg) argument
188 nsp32_mmio_index_write1(unsigned long base, unsigned int reg, unsigned char val) argument
201 nsp32_mmio_index_read2(unsigned long base, unsigned int reg) argument
213 nsp32_mmio_index_write2(unsigned long base, unsigned int reg, unsigned short val) argument
228 nsp32_multi_read4(unsigned int base, unsigned int reg, void *buf, unsigned long count) argument
236 nsp32_fifo_read(unsigned int base, void *buf, unsigned long count) argument
243 nsp32_multi_write4(unsigned int base, unsigned int reg, void *buf, unsigned long count) argument
251 nsp32_fifo_write(unsigned int base, void *buf, unsigned long count) argument
[all...]
H A Daha1740.h18 #define HID0(base) (base + 0x0)
19 #define HID1(base) (base + 0x1)
20 #define HID2(base) (base + 0x2)
21 #define HID3(base) (base + 0x3)
22 #define EBCNTRL(base) (base
[all...]
H A Dnsp32_debug.c228 static void nsp32_print_register(int base) argument
233 printk("Phase=0x%x, ", nsp32_read1(base, SCSI_BUS_MONITOR));
234 printk("OldPhase=0x%x, ", nsp32_index_read1(base, OLD_SCSI_PHASE));
235 printk("syncreg=0x%x, ", nsp32_read1(base, SYNC_REG));
236 printk("ackwidth=0x%x, ", nsp32_read1(base, ACK_WIDTH));
237 printk("sgtpaddr=0x%lx, ", nsp32_read4(base, SGT_ADR));
238 printk("scsioutlatch=0x%x, ", nsp32_read1(base, SCSI_OUT_LATCH_TARGET_ID));
239 printk("msgout=0x%lx, ", nsp32_read4(base, SCSI_MSG_OUT));
240 printk("miscrd=0x%x, ", nsp32_index_read2(base, MISC_WR));
241 printk("seltimeout=0x%x, ", nsp32_read2(base, SEL_TIME_OU
[all...]
/drivers/usb/dwc3/
H A Dio.h44 static inline u32 dwc3_readl(void __iomem *base, u32 offset) argument
46 return readl(base + offset);
49 static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) argument
51 writel(value, base + offset);
/drivers/usb/host/
H A Dalchemy-common.c5 * area. Au1550 has OHCI on different base address. No need to handle
95 static inline void __au1300_usb_phyctl(void __iomem *base, int enable) argument
99 r = __raw_readl(base + USB_DWC_CTRL2);
100 s = __raw_readl(base + USB_DWC_CTRL3);
109 __raw_writel(r, base + USB_DWC_CTRL2);
115 __raw_writel(r, base + USB_DWC_CTRL2);
120 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id) argument
125 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */
128 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */
131 __raw_writel(r, base
160 __au1300_ehci_control(void __iomem *base, int enable) argument
201 __au1300_udc_control(void __iomem *base, int enable) argument
232 __au1300_otg_control(void __iomem *base, int enable) argument
264 void __iomem *base = local
292 void __iomem *base = local
313 __au1200_ohci_control(void __iomem *base, int enable) argument
327 __au1200_ehci_control(void __iomem *base, int enable) argument
343 __au1200_udc_control(void __iomem *base, int enable) argument
373 void __iomem *base = local
404 void __iomem *base = local
413 void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg); local
429 void __iomem *base = (void __iomem *)KSEG1ADDR(rb); local
506 void __iomem *base = (void __iomem *)KSEG1ADDR(br); local
523 void __iomem *base = local
543 void __iomem *base = local
[all...]
H A Dpci-quirks.h5 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
6 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
/drivers/scsi/pcmcia/
H A Dnsp_io.h15 static inline void nsp_write(unsigned int base,
18 static inline unsigned char nsp_read(unsigned int base,
30 static inline void nsp_write(unsigned int base, argument
34 outb(val, (base + index));
37 static inline unsigned char nsp_read(unsigned int base, argument
40 return inb(base + index);
75 static inline void nsp_fifo8_read(unsigned int base, argument
80 nsp_multi_read_1(base, FIFODATA, buf, count);
94 static inline void nsp_fifo16_read(unsigned int base, argument
99 nsp_multi_read_2(base, FIFODAT
113 nsp_fifo32_read(unsigned int base, void *buf, unsigned long count) argument
132 nsp_fifo8_write(unsigned int base, void *buf, unsigned long count) argument
150 nsp_fifo16_write(unsigned int base, void *buf, unsigned long count) argument
168 nsp_fifo32_write(unsigned int base, void *buf, unsigned long count) argument
178 nsp_mmio_write(unsigned long base, unsigned int index, unsigned char val) argument
187 nsp_mmio_read(unsigned long base, unsigned int index) argument
197 nsp_mmio_index_read(unsigned long base, unsigned int reg) argument
207 nsp_mmio_index_write(unsigned long base, unsigned int reg, unsigned char val) argument
219 nsp_mmio_multi_read_4(unsigned long base, unsigned int Register, void *buf, unsigned long count) argument
237 nsp_mmio_fifo32_read(unsigned int base, void *buf, unsigned long count) argument
245 nsp_mmio_multi_write_4(unsigned long base, unsigned int Register, void *buf, unsigned long count) argument
263 nsp_mmio_fifo32_write(unsigned int base, void *buf, unsigned long count) argument
[all...]
/drivers/isdn/hardware/avm/
H A Davmcard.h219 static inline unsigned char b1outp(unsigned int base, argument
223 outb(value, base + offset);
224 return inb(base + B1_ANALYSE);
228 static inline int b1_rx_full(unsigned int base) argument
230 return inb(base + B1_INSTAT) & 0x1;
233 static inline unsigned char b1_get_byte(unsigned int base) argument
236 while (!b1_rx_full(base) && time_before(jiffies, stop));
237 if (b1_rx_full(base))
238 return inb(base + B1_READ);
239 printk(KERN_CRIT "b1lli(0x%x): rx not full after 1 second\n", base);
243 b1_get_word(unsigned int base) argument
253 b1_tx_empty(unsigned int base) argument
258 b1_put_byte(unsigned int base, unsigned char val) argument
264 b1_save_put_byte(unsigned int base, unsigned char val) argument
273 b1_put_word(unsigned int base, unsigned int val) argument
281 b1_get_slice(unsigned int base, unsigned char *dp) argument
291 b1_put_slice(unsigned int base, unsigned char *dp, unsigned int len) argument
300 b1_wr_reg(unsigned int base, unsigned int reg, unsigned int value) argument
309 b1_rd_reg(unsigned int base, unsigned int reg) argument
318 b1_reset(unsigned int base) argument
330 b1_disable_irq(unsigned int base) argument
337 b1_set_test_bit(unsigned int base, enum avmcardtype cardtype, int onoff) argument
344 b1_get_test_bit(unsigned int base, enum avmcardtype cardtype) argument
386 t1outp(unsigned int base, unsigned short offset, unsigned char value) argument
393 t1inp(unsigned int base, unsigned short offset) argument
399 t1_isfastlink(unsigned int base) argument
404 t1_fifostatus(unsigned int base) argument
409 t1_get_slice(unsigned int base, unsigned char *dp) argument
462 t1_put_slice(unsigned int base, unsigned char *dp, unsigned int len) argument
495 t1_disable_irq(unsigned int base) argument
500 t1_reset(unsigned int base) argument
512 b1_setinterrupt(unsigned int base, unsigned irq, enum avmcardtype cardtype) argument
[all...]
/drivers/ata/
H A Dpata_bf54x.c77 #define ATAPI_GET_CONTROL(base)\
78 bfin_read16(base + ATAPI_OFFSET_CONTROL)
79 #define ATAPI_SET_CONTROL(base, val)\
80 bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
81 #define ATAPI_GET_STATUS(base)\
82 bfin_read16(base + ATAPI_OFFSET_STATUS)
83 #define ATAPI_GET_DEV_ADDR(base)\
84 bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
85 #define ATAPI_SET_DEV_ADDR(base, val)\
86 bfin_write16(base
292 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
371 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
480 wait_complete(void __iomem *base, unsigned short mask) argument
504 write_atapi_register(void __iomem *base, unsigned long ata_reg, unsigned short value) argument
541 read_atapi_register(void __iomem *base, unsigned long ata_reg) argument
579 write_atapi_data(void __iomem *base, int len, unsigned short *buf) argument
624 read_atapi_data(void __iomem *base, int len, unsigned short *buf) argument
671 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
728 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
742 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
773 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
787 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
801 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
821 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
836 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
914 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
968 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
999 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
1048 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
1132 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
1158 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
1195 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
1228 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; local
1464 void __iomem *base = (void __iomem *)host->ports[0]->ioaddr.ctl_addr; local
[all...]
/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_fw_defs.h13 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[148].base)
15 (IRO[147].base + ((assertListEntry) * IRO[147].m1))
17 (IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \
20 (IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \
23 (IRO[159].base + ((funcId) * IRO[159].m1))
25 (IRO[149].base + ((funcId) * IRO[149].m1))
26 #define CSTORM_IGU_MODE_OFFSET (IRO[157].base)
28 (IRO[316].base + ((pfId) * IRO[316].m1))
30 (IRO[317].base + ((pfId) * IRO[317].m1))
32 (IRO[309].base
[all...]
/drivers/s390/block/
H A Ddasd_ioctl.c46 struct dasd_device *base; local
51 base = dasd_device_from_gendisk(bdev->bd_disk);
52 if (!base)
55 dasd_enable_device(base);
59 (loff_t)get_capacity(base->block->gdp) << 9);
61 dasd_put_device(base);
72 struct dasd_device *base; local
77 base = dasd_device_from_gendisk(bdev->bd_disk);
78 if (!base)
88 dasd_set_target_state(base, DASD_STATE_BASI
106 struct dasd_device *base; local
127 struct dasd_device *base; local
152 struct dasd_device *base; local
205 struct dasd_device *base; local
314 struct dasd_device *base; local
398 struct dasd_device *base; local
438 struct dasd_device *base; local
[all...]
H A Ddasd_genhd.c33 struct dasd_device *base; local
37 base = block->base;
38 if (base->devindex >= DASD_PER_MAJOR)
47 gdp->first_minor = base->devindex << DASD_PARTN_BITS;
49 gdp->driverfs_dev = &base->cdev->dev;
59 if (base->devindex > 25) {
60 if (base->devindex > 701) {
61 if (base->devindex > 18277)
63 'a'+(((base
[all...]
/drivers/atm/
H A Dnicstarmac.c110 writel((val),(base)+(reg))
112 readl((base)+(reg))
121 u_int32_t nicstar_read_eprom_status(virt_addr_t base)
128 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
131 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
141 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
143 rbyte |= (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)
145 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
149 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2);
161 static u_int8_t read_eprom_byte(virt_addr_t base, u_int8_ argument
206 nicstar_init_eprom(virt_addr_t base) argument
238 nicstar_read_eprom(virt_addr_t base, u_int8_t prom_offset, u_int8_t * buffer, u_int32_t nbytes) argument
[all...]
/drivers/gpu/drm/i915/
H A Di915_gem_debug.c46 if (obj->base.dev != dev ||
47 !atomic_read(&obj->base.refcount.refcount)) {
52 (obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) {
56 obj->base.read_domains);
58 } else if (obj->base.write_domain && list_empty(&obj->gpu_write_list)) {
61 obj->base.write_domain,
68 if (obj->base.dev != dev ||
69 !atomic_read(&obj->base.refcount.refcount)) {
74 (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0 ||
79 obj->base
[all...]
/drivers/mtd/chips/
H A Dcfi_probe.c27 static int cfi_probe_chip(struct map_info *map, __u32 base,
38 #define xip_allowed(base, map) \
40 (void) map_read(map, base); \
45 #define xip_enable(base, map, cfi) \
47 cfi_qry_mode_off(base, map, cfi); \
48 xip_allowed(base, map); \
51 #define xip_disable_qry(base, map, cfi) \
54 cfi_qry_mode_on(base, map, cfi); \
60 #define xip_allowed(base, map) do { } while (0)
61 #define xip_enable(base, ma
71 cfi_probe_chip(struct map_info *map, __u32 base, unsigned long *chip_map, struct cfi_private *cfi) argument
158 __u32 base = 0; local
[all...]
/drivers/ide/
H A Dpalm_bk3710.c77 static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev, argument
92 val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
94 writel(val32, base + BK3710_UDMASTB);
97 val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
99 writel(val32, base + BK3710_UDMATRP);
102 val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
104 writel(val32, base + BK3710_UDMAENV);
107 val16 = readw(base + BK3710_UDMACTL) | (1 << dev);
108 writew(val16, base + BK3710_UDMACTL);
111 static void palm_bk3710_setdmamode(void __iomem *base, unsigne argument
143 palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate, unsigned int dev, unsigned int cycletime, unsigned int mode) argument
194 void __iomem *base = (void *)hwif->dma_base; local
212 void __iomem *base = (void *)hwif->dma_base; local
223 palm_bk3710_chipinit(void __iomem *base) argument
318 void __iomem *base; local
[all...]
H A Dide-legacy.c9 unsigned long base, ctl; local
13 base = 0x1f0;
17 base = 0x170;
22 if (!request_region(base, 8, d->name)) {
24 d->name, base, base + 7);
31 release_region(base, 8);
35 ide_std_init_ports(hw, base, ctl);
/drivers/gpio/
H A Dgpio-samsung.c54 void __iomem *reg = chip->base + 0x08;
69 void __iomem *reg = chip->base + 0x08;
123 void __iomem *reg = chip->base + 0x08;
141 void __iomem *reg = chip->base + 0x08;
211 void __iomem *reg = chip->base;
246 con = __raw_readl(chip->base);
274 void __iomem *reg = chip->base;
309 void __iomem *reg = chip->base;
339 void __iomem *reg = chip->base;
379 con = __raw_readl(chip->base);
532 void __iomem *base = ourchip->base; local
551 void __iomem *base = ourchip->base; local
595 void __iomem *base = ourchip->base; local
611 void __iomem *base = ourchip->base; local
661 void __iomem *base = ourchip->base; local
683 void __iomem *base = ourchip->base; local
726 void __iomem *base = ourchip->base; local
758 void __iomem *base = ourchip->base; local
794 void __iomem *base = ourchip->base; local
841 void __iomem *base = ourchip->base; local
941 s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip, int nr_chips, void __iomem *base) argument
968 samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip, int nr_chips, void __iomem *base, unsigned int offset) argument
1005 samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip, int nr_chips, void __iomem *base) argument
2691 exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip, u64 base, u64 offset) argument
2712 exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip, u64 base, u64 offset) argument
[all...]
/drivers/gpu/drm/gma500/
H A Dframebuffer.h31 struct drm_framebuffer base; member in struct:psb_framebuffer
42 #define to_psb_fb(x) container_of(x, struct psb_framebuffer, base)
/drivers/gpu/drm/nouveau/
H A Dnouveau_fb.h31 struct drm_framebuffer base; member in struct:nouveau_framebuffer
42 return container_of(fb, struct nouveau_framebuffer, base);
/drivers/scsi/aacraid/
H A Dnark.c48 iounmap(dev->base);
49 dev->base = NULL;
52 dev->scsi_host_ptr->base = pci_resource_start(dev->pdev, 2);
56 dev->base = NULL;
59 dev->base = ioremap(dev->scsi_host_ptr->base, size);
60 if (dev->base == NULL) {
65 dev->IndexRegs = &((struct rx_registers __iomem *)dev->base)->IndexRegs;
/drivers/video/matrox/
H A Dmatroxfb_crtc2.h15 unsigned long base; /* physical */ member in struct:matroxfb_dh_fb_info::__anon5846
24 unsigned long base; member in struct:matroxfb_dh_fb_info::__anon5847

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