Searched refs:TII (Results 26 - 50 of 193) sorted by relevance

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/external/llvm/lib/Target/Mips/
H A DMips16FrameLowering.cpp33 const Mips16InstrInfo &TII = local
47 TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
52 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
59 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
73 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
82 const Mips16InstrInfo &TII = local
91 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
96 TII.restoreFrame(Mips::SP, StackSize, MBB, MBBI);
152 const Mips16InstrInfo &TII = local
155 TII
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H A DMipsSERegisterInfo.cpp45 : MipsRegisterInfo(ST), TII(I) {}
114 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm);
115 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
H A DMips16RegisterInfo.cpp47 : MipsRegisterInfo(ST), TII(I) {}
70 TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
71 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
137 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
H A DMipsSEFrameLowering.cpp49 const MipsSEInstrInfo &TII = local
69 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
74 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
91 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
128 TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false,
135 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel2);
147 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
152 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
166 const MipsSEInstrInfo &TII = local
183 BuildMI(MBB, I, dl, TII
219 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); local
256 const MipsSEInstrInfo &TII = local
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/external/llvm/lib/Target/Hexagon/
H A DHexagonFixupHwLoops.cpp161 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); local
169 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
173 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFRI), Scratch)
175 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
179 BuildMI(*MBB, MII, DL, TII->get(Hexagon::CONST32_Label), Scratch)
181 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::SA0)
H A DHexagonRegisterInfo.h47 const HexagonInstrInfo &TII; member in struct:llvm::HexagonRegisterInfo
/external/llvm/lib/Target/MBlaze/
H A DMBlazeFrameLowering.cpp225 const MBlazeInstrInfo &TII = local
255 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), r)
263 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R17)
266 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R18)
272 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::MFS), MBlaze::R11)
274 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R11)
277 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R11)
279 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::MTS), MBlaze::RMSR)
284 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R18)
287 BuildMI(MEXT, MEXTI, EXTDL, TII
344 const MBlazeInstrInfo &TII = local
391 const MBlazeInstrInfo &TII = local
433 const MBlazeInstrInfo &TII = local
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H A DMBlazeRegisterInfo.h40 const TargetInstrInfo &TII; member in struct:llvm::MBlazeRegisterInfo
/external/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp52 , Threshold(4), TM(0), TII(0) {}
81 const TargetInstrInfo *TII; member in struct:__anon9842::PadShortFunc
103 TII = TM->getInstrInfo();
193 CyclesToEnd += TII->getInstrLatency(TM->getInstrItineraryData(), MI);
209 BuildMI(*MBB, MBBI, DL, TII->get(X86::NOOP));
210 BuildMI(*MBB, MBBI, DL, TII->get(X86::NOOP));
H A DX86FrameLowering.cpp149 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
654 const X86InstrInfo &TII = *TM.getInstrInfo();
715 TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)),
759 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
766 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
788 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
795 BuildMI(MBB, MBBI, DL, TII
146 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned StackPtr, int64_t NumBytes, bool Is64Bit, bool IsLP64, bool UseLEA, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) argument
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/external/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.h30 const TargetInstrInfo &TII; member in struct:llvm::MSP430RegisterInfo
/external/llvm/lib/Target/R600/
H A DSIRegisterInfo.cpp25 TII(tii)
/external/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.h30 const TargetInstrInfo &TII; member in struct:llvm::SparcRegisterInfo
H A DSparcRegisterInfo.cpp33 : SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) {
84 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
86 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
/external/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp32 const TargetInstrInfo *TII; member in struct:__anon9459::ExpandPostRA
101 MI->setDesc(TII->get(TargetOpcode::KILL));
112 MI->setDesc(TII->get(TargetOpcode::KILL));
120 TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
139 MI->setDesc(TII->get(TargetOpcode::KILL));
154 MI->setDesc(TII->get(TargetOpcode::KILL));
164 TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
185 TII = MF.getTarget().getInstrInfo();
202 if (TII->expandPostRAPseudo(MI)) {
H A DBranchFolding.cpp148 if (!TII->isUnpredicatedTerminator(I))
182 TII = tii;
199 if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true))
397 TII->ReplaceTailWithBranchTo(OldInst, NewDest);
410 if (!TII->isLegalToSplitMBBAt(CurMBB, BBI1))
458 const TargetInstrInfo *TII) {
465 !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true)) {
468 if (!TII->ReverseBranchCondition(Cond)) {
469 TII->RemoveBranch(*CurMBB);
470 TII
457 FixTail(MachineBasicBlock *CurMBB, MachineBasicBlock *SuccBB, const TargetInstrInfo *TII) argument
1473 findHoistingInsertPosAndDeps(MachineBasicBlock *MBB, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, SmallSet<unsigned,4> &Uses, SmallSet<unsigned,4> &Defs) argument
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H A DIfConversion.cpp155 const TargetInstrInfo *TII; member in class:__anon9462::IfConverter
212 return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra,
222 TII->isProfitableToIfCvt(TBB, TCycle, TExtra, FBB, FCycle, FExtra,
266 TII = MF.getTarget().getInstrInfo();
271 if (!TII) return false;
279 BFChange = BF.OptimizeFunction(MF, TII,
413 BF.OptimizeFunction(MF, TII,
439 if (!TII->ReverseBranchCondition(BBI.BrCond)) {
440 TII->RemoveBranch(*BBI.BB);
441 TII
948 InsertUncondBranch(MachineBasicBlock *BB, MachineBasicBlock *ToBB, const TargetInstrInfo *TII) argument
1413 MaySpeculate(const MachineInstr *MI, SmallSet<unsigned, 4> &LaterRedefs, const TargetInstrInfo *TII) argument
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/external/llvm/lib/Target/ARM/
H A DThumb1RegisterInfo.cpp78 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
95 const TargetInstrInfo &TII,
117 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
120 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
122 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
131 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
171 int NumBytes, const TargetInstrInfo &TII,
231 TII, MRI, MIFlags);
241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
247 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII
90 emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags = MachineInstr::NoFlags) argument
167 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags) argument
301 emitThumbConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Imm, const TargetInstrInfo &TII, const Thumb1RegisterInfo& MRI, DebugLoc dl) argument
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H A DARMFrameLowering.cpp93 const ARMBaseInstrInfo &TII,
121 DebugLoc dl, const ARMBaseInstrInfo &TII,
126 Pred, PredReg, TII, MIFlags);
129 Pred, PredReg, TII, MIFlags);
139 const ARMBaseInstrInfo &TII = local
163 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize,
168 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
224 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
266 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
298 TII
92 isCSRestore(MachineInstr *MI, const ARMBaseInstrInfo &TII, const uint16_t *CSRegs) argument
119 emitSPUpdate(bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, const ARMBaseInstrInfo &TII, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags, ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) argument
354 const ARMBaseInstrInfo &TII = local
585 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
653 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
736 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
895 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
1028 GetFunctionSizeInBytes(const MachineFunction &MF, const ARMBaseInstrInfo &TII) argument
1159 const ARMBaseInstrInfo &TII = local
1388 const ARMBaseInstrInfo &TII = local
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H A DThumb2RegisterInfo.cpp48 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
/external/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp53 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
89 emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumInitialBytes,
96 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
119 emitRegUpdate(MBB, MBBI, DL, TII, AArch64::X29, AArch64::XSP,
132 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
148 emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumResidualBytes,
163 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
177 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
199 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
215 MIB = BuildMI(MBB, MBBI, DL, TII
358 const AArch64InstrInfo &TII = local
431 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
600 const AArch64InstrInfo &TII = local
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H A DAArch64InstrInfo.h96 const AArch64InstrInfo &TII);
100 DebugLoc dl, const TargetInstrInfo &TII,
106 DebugLoc dl, const TargetInstrInfo &TII,
H A DAArch64RegisterInfo.h29 const AArch64InstrInfo &TII; member in struct:llvm::AArch64RegisterInfo
/external/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.h46 const TargetInstrInfo &TII; member in class:llvm::PPCHazardRecognizer970
67 PPCHazardRecognizer970(const TargetInstrInfo &TII);
H A DPPCRegisterInfo.cpp56 Subtarget(ST), TII(tii) {
213 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
217 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
221 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
229 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
234 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
239 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
244 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
250 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
255 BuildMI(MBB, II, dl, TII
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