Searched defs:SrcReg (Results 1 - 25 of 75) sorted by relevance

123

/external/llvm/lib/CodeGen/
H A DPHIEliminationUtils.cpp17 // findCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg
19 // SrcReg, but before any subsequent point where control flow might jump out of
23 unsigned SrcReg) {
37 for (MachineInstr &RI : MRI.reg_instructions(SrcReg)) {
22 findPHICopyInsertPoint(MachineBasicBlock* MBB, MachineBasicBlock* SuccMBB, unsigned SrcReg) argument
H A DOptimizePHIs.cpp103 unsigned SrcReg = MI->getOperand(i).getReg(); local
104 if (SrcReg == DstReg)
106 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
124 SingleValReg = SrcReg;
H A DRegisterCoalescer.h35 /// SrcReg - the virtual register that will be coalesced into dstReg.
36 unsigned SrcReg; member in class:llvm::CoalescerPair
42 /// SrcIdx - The sub-register index of the old SrcReg in the new coalesced
52 /// Flipped - True when DstReg and SrcReg are reversed from the original
58 /// SrcReg and DstReg.
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
77 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible
105 unsigned getSrcReg() const { return SrcReg; }
111 /// getSrcIdx - Return the subregister index that SrcReg wil
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIInstrInfo.cpp39 unsigned DestReg, unsigned SrcReg,
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
49 .addReg(SrcReg, getKillRegState(KillSrc));
37 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
H A DAMDGPUInstrInfo.cpp37 unsigned &SrcReg, unsigned &DstReg,
124 unsigned SrcReg, bool isKill,
36 isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const argument
122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIInstrInfo.cpp39 unsigned DestReg, unsigned SrcReg,
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
49 .addReg(SrcReg, getKillRegState(KillSrc));
37 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
H A DAMDGPUInstrInfo.cpp37 unsigned &SrcReg, unsigned &DstReg,
124 unsigned SrcReg, bool isKill,
36 isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const argument
122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp42 unsigned DestReg, unsigned SrcReg,
45 .addReg(SrcReg, getKillRegState(KillSrc)));
46 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
52 unsigned SrcReg, bool isKill, int FI,
56 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
57 isARMLowRegister(SrcReg))) && "Unknown regclass!");
60 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
61 isARMLowRegister(SrcReg))) {
73 .addReg(SrcReg, getKillRegState(isKill))
40 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
51 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DThumb2InstrInfo.cpp115 unsigned DestReg, unsigned SrcReg,
118 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
119 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
122 .addReg(SrcReg, getKillRegState(KillSrc)));
127 unsigned SrcReg, bool isKill, int FI,
145 .addReg(SrcReg, getKillRegState(isKill))
155 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
158 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
159 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
165 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKil
113 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
126 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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H A DThumb2ITBlockPass.cpp120 unsigned SrcReg = MI->getOperand(1).getReg(); local
123 if (Uses.count(DstReg) || Defs.count(SrcReg))
/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp87 // STriw_pred [R30], ofst, SrcReg;
93 int SrcReg = MI->getOperand(2).getReg(); local
94 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
105 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
114 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
123 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
H A DHexagonPeephole.cpp143 unsigned SrcReg = Src.getReg(); local
146 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
150 PeepholeMap[DstReg] = SrcReg;
165 unsigned SrcReg = Src2.getReg(); local
166 PeepholeMap[DstReg] = SrcReg;
182 unsigned SrcReg = Src1.getReg(); local
184 std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/);
194 unsigned SrcReg = Src.getReg(); local
197 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
201 PeepholeMap[DstReg] = SrcReg;
217 unsigned SrcReg = Src.getReg(); local
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/external/chromium_org/third_party/mesa/src/src/mesa/main/
H A Datifragshader.h55 struct atifragshader_src_register SrcReg[2][3]; member in struct:atifs_instruction
/external/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp39 unsigned SrcReg, bool isKill, int FrameIdx,
56 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
60 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
93 unsigned DestReg, unsigned SrcReg,
96 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
98 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
104 .addReg(SrcReg, getKillRegState(KillSrc));
37 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
91 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
/external/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp37 unsigned DestReg, unsigned SrcReg, bool KillSrc) const {
40 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
47 .addReg(SrcReg, getKillRegState(KillSrc));
50 .addReg(SrcReg, getKillRegState(KillSrc));
53 .addReg(SrcReg, getKillRegState(KillSrc));
56 .addReg(SrcReg, getKillRegState(KillSrc));
59 .addReg(SrcReg, getKillRegState(KillSrc));
62 .addReg(SrcReg, getKillRegState(KillSrc));
68 bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, argument
83 SrcReg
35 copyPhysReg( MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
[all...]
/external/llvm/lib/Target/R600/
H A DSIFixSGPRCopies.cpp182 unsigned SrcReg = Copy.getOperand(1).getReg(); local
187 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
189 MRI.getRegClass(SrcReg) == &AMDGPU::VReg_1RegClass)
192 SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg);
H A DR600InstrInfo.cpp51 unsigned DestReg, unsigned SrcReg,
56 (AMDGPU::R600_Reg128RegClass.contains(SrcReg) ||
57 AMDGPU::R600_Reg128VerticalRegClass.contains(SrcReg))) {
61 (AMDGPU::R600_Reg64RegClass.contains(SrcReg) ||
62 AMDGPU::R600_Reg64VerticalRegClass.contains(SrcReg))) {
71 RI.getSubReg(SrcReg, SubRegIndex))
77 DestReg, SrcReg);
1325 unsigned DstReg, unsigned SrcReg) const {
1326 return buildDefaultInstruction(*MBB, I, AMDGPU::MOV, DstReg, SrcReg);
49 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
/external/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp178 unsigned SrcReg = MI.getOperand(2).getReg(); local
179 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
180 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
H A DSparcInstrInfo.cpp283 unsigned DestReg, unsigned SrcReg,
295 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
297 .addReg(SrcReg, getKillRegState(KillSrc));
298 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
300 .addReg(SrcReg, getKillRegState(KillSrc));
301 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
304 .addReg(SrcReg, getKillRegState(KillSrc));
311 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
315 .addReg(SrcReg, getKillRegState(KillSrc));
339 unsigned Src = TRI->getSubReg(SrcReg, subRegId
281 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
351 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...]
/external/mesa3d/src/mesa/main/
H A Datifragshader.h55 struct atifragshader_src_register SrcReg[2][3]; member in struct:atifs_instruction
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
H A Dradeon_program.h66 struct rc_src_register SrcReg[2]; member in struct:rc_presub_instruction
78 struct rc_src_register SrcReg[3]; member in struct:rc_sub_instruction
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp87 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
89 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
94 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
120 } else if (DestReg != SrcReg)
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
172 VRBase = SrcReg;
177 VRBase).addReg(SrcReg);
491 unsigned SrcReg, DstReg, DefSubIdx;
493 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
495 TRC == MRI->getRegClass(SrcReg)) {
86 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) argument
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp134 unsigned SrcReg = I->getOperand(0).getReg(); local
135 unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64;
137 .addReg(SrcReg);
/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp343 unsigned DestReg, unsigned SrcReg,
346 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
350 .addReg(SrcReg, getKillRegState(KillSrc))
355 if (GRDest && SrcReg == XCore::SP) {
362 .addReg(SrcReg, getKillRegState(KillSrc));
370 unsigned SrcReg, bool isKill,
386 .addReg(SrcReg, getKillRegState(isKill))
341 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
368 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_program.h66 struct rc_src_register SrcReg[2]; member in struct:rc_presub_instruction
78 struct rc_src_register SrcReg[3]; member in struct:rc_sub_instruction

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