/external/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 67 unsigned DestReg, int FrameIdx, 83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); 86 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); 93 unsigned DestReg, unsigned SrcReg, 96 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) 98 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) 103 BuildMI(MBB, I, DL, get(Opc), DestReg) 65 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 91 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCopyToCombine.cpp | 93 void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg, 96 void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg, 99 void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg, 102 void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg, 121 unsigned DestReg = MI->getOperand(0).getReg(); local 123 return Hexagon::IntRegsRegClass.contains(DestReg) && 131 unsigned DestReg = MI->getOperand(0).getReg(); local 134 return Hexagon::IntRegsRegClass.contains(DestReg) && 149 unsigned DestReg = MI->getOperand(0).getReg(); local 150 return Hexagon::IntRegsRegClass.contains(DestReg); 221 isUnsafeToMoveAcross(MachineInstr *I, unsigned UseReg, unsigned DestReg, const TargetRegisterInfo *TRI) argument [all...] |
H A D | HexagonInstrInfo.cpp | 418 unsigned DestReg, unsigned SrcReg, 420 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { 421 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg); 424 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) { 425 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg); 428 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) { 431 DestReg).addReg(SrcReg).addReg(SrcReg); 434 if (Hexagon::DoubleRegsRegClass.contains(DestReg) && 437 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) { 439 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg, 416 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 520 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 550 loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument [all...] |
H A D | HexagonInstrInfo.h | 80 unsigned DestReg, unsigned SrcReg, 96 unsigned DestReg, int FrameIndex, 100 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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/external/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 326 unsigned DestReg = createResultReg(RC); local 328 EmitInst(Mips::MTC1, DestReg).addReg(TempReg); 329 return DestReg; 332 unsigned DestReg = createResultReg(RC); local 336 EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); 337 return DestReg; 347 unsigned DestReg = createResultReg(RC); local 353 EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress( 355 return DestReg;
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H A D | Mips16InstrInfo.h | 48 unsigned DestReg, unsigned SrcReg, 60 unsigned DestReg, int FrameIndex,
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H A D | Mips16InstrInfo.cpp | 66 unsigned DestReg, unsigned SrcReg, 70 if (Mips::CPU16RegsRegClass.contains(DestReg) && 73 else if (Mips::GPR32RegClass.contains(DestReg) && 77 (Mips::CPU16RegsRegClass.contains(DestReg))) 81 (Mips::CPU16RegsRegClass.contains(DestReg))) 89 if (DestReg) 90 MIB.addReg(DestReg, RegState::Define); 115 unsigned DestReg, int FI, const TargetRegisterClass *RC, 125 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset) 64 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 114 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.cpp | 120 unsigned DestReg = MI->getOperand(0).getReg(); local 122 bool DestIsHigh = isHighReg(DestReg); 128 DestReg, SrcReg, SystemZ::LR, 32, 131 MI->getOperand(1).setReg(DestReg); 158 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg 164 DebugLoc DL, unsigned DestReg, 168 bool DestIsHigh = isHighReg(DestReg); 177 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg) 182 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) 162 emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, unsigned LowLowOpcode, unsigned Size, bool KillSrc) const argument 553 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 606 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 691 unsigned DestReg = Dest.getReg(); local [all...] |
H A D | SystemZInstrInfo.h | 129 DebugLoc DL, unsigned DestReg, unsigned SrcReg, 170 DebugLoc DL, unsigned DestReg, unsigned SrcReg, 179 unsigned DestReg, int FrameIdx,
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64A57FPLoadBalancing.cpp | 590 unsigned DestReg = MI->getOperand(0).getReg(); local 593 << TRI->getName(DestReg) << " at " << *MI); 595 auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg)); 596 ActiveChains[DestReg] = G.get(); 603 unsigned DestReg = MI->getOperand(0).getReg(); local 608 if (DestReg != AccumReg) 623 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); 625 if (DestReg != AccumReg) { 626 ActiveChains[DestReg] = ActiveChains[AccumReg]; 638 << TRI->getName(DestReg) << "\ [all...] |
H A D | AArch64InstrInfo.h | 104 DebugLoc DL, unsigned DestReg, unsigned SrcReg, 108 DebugLoc DL, unsigned DestReg, unsigned SrcReg, 118 MachineBasicBlock::iterator MBBI, unsigned DestReg, 165 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg 170 DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb1RegisterInfo.h | 40 DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
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H A D | ARMBaseInstrInfo.h | 108 DebugLoc DL, unsigned DestReg, unsigned SrcReg, 119 unsigned DestReg, int FrameIndex, 126 unsigned DestReg, unsigned SubIdx, 402 unsigned DestReg, unsigned BaseReg, int NumBytes, 408 unsigned DestReg, unsigned BaseReg, int NumBytes, 413 unsigned DestReg, unsigned BaseReg,
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H A D | ARMBaseInstrInfo.cpp | 664 unsigned DestReg, unsigned SrcReg, 666 bool GPRDest = ARM::GPRRegClass.contains(DestReg); 670 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 675 bool SPRDest = ARM::SPRRegClass.contains(DestReg); 685 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 687 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 691 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 705 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { 709 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { 714 } else if (ARM::DPairRegClass.contains(DestReg, SrcRe 662 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 987 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 1290 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument 1755 unsigned DestReg = MI->getOperand(0).getReg(); local 1840 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 343 unsigned DestReg, unsigned SrcReg, 345 bool GRDest = XCore::GRRegsRegClass.contains(DestReg); 349 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) 356 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); 360 if (DestReg == XCore::SP && GRSrc) { 394 unsigned DestReg, int FrameIndex, 408 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) 341 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 392 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 626 unsigned DestReg, 684 BuildMI(MBB, MI, dl, get(OpCode), DestReg) 691 unsigned DestReg, unsigned SrcReg, 696 if (PPC::F8RCRegClass.contains(DestReg) && 699 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass); 704 DestReg = SuperReg; 705 } else if (PPC::VRRCRegClass.contains(DestReg) && 708 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass); 713 DestReg = SuperReg; 715 PPC::VSLRCRegClass.contains(DestReg)) { 624 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc dl, unsigned DestReg, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg) const argument 689 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 885 LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs, bool &NonRI, bool &SpillsVRS) const argument 945 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
H A D | PPCInstrInfo.h | 77 unsigned DestReg, int FrameIdx, 151 unsigned DestReg, unsigned SrcReg, 162 unsigned DestReg, int FrameIndex,
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600InstrInfo.cpp | 51 unsigned DestReg, unsigned SrcReg, 54 if (AMDGPU::R600_Reg128RegClass.contains(DestReg) 59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) 63 .addReg(DestReg, RegState::Define | RegState::Implicit); 68 assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg) 71 BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg) 49 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
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H A D | AMDGPUInstrInfo.h | 75 unsigned DestReg, unsigned SrcReg, 85 unsigned DestReg, int FrameIndex,
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600InstrInfo.cpp | 51 unsigned DestReg, unsigned SrcReg, 54 if (AMDGPU::R600_Reg128RegClass.contains(DestReg) 59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) 63 .addReg(DestReg, RegState::Define | RegState::Implicit); 68 assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg) 71 BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg) 49 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
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H A D | AMDGPUInstrInfo.h | 75 unsigned DestReg, unsigned SrcReg, 85 unsigned DestReg, int FrameIndex,
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUInstrInfo.h | 79 unsigned DestReg, unsigned SrcReg, 91 unsigned DestReg, int FrameIndex,
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H A D | SIInstrInfo.h | 67 unsigned DestReg, unsigned SrcReg, 78 unsigned DestReg, int FrameIndex,
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 206 unsigned DestReg, unsigned SubIdx, 266 unsigned DestReg, unsigned SrcReg, 283 unsigned DestReg, int FrameIndex, 287 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcRegisterInfo.cpp | 190 unsigned DestReg = MI.getOperand(0).getReg(); local 191 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); 192 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
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