Searched refs:MI (Results 76 - 100 of 514) sorted by relevance

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/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp68 uint64_t getBinaryCodeForInstr(const MCInst &MI,
74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigne
191 getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
264 getCCOutOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
273 getSOImmOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
308 getT2SOImmOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
341 getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
437 NEONThumb2DataIPostEncoder(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const argument
457 NEONThumb2LoadStorePostEncoder(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const argument
471 NEONThumb2DupPostEncoder(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const argument
484 NEONThumb2V8PostEncoder(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const argument
497 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const argument
509 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
538 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
567 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) argument
605 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
618 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
630 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
642 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
654 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
664 HasConditionalBranch(const MCInst &MI) argument
683 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
697 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
713 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
728 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
741 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
771 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
812 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
832 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
845 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &, const MCSubtargetInfo &STI) const argument
860 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
912 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
944 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
985 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
998 getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1054 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1088 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1103 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1126 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1138 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1158 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1195 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1211 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1226 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1237 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1276 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1324 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
[all...]
/external/llvm/lib/CodeGen/
H A DMachineSink.cpp82 bool isWorthBreakingCriticalEdge(MachineInstr *MI,
85 MachineBasicBlock *SplitCriticalEdge(MachineInstr *MI,
89 bool SinkInstruction(MachineInstr *MI, bool &SawStore);
93 MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, MachineBasicBlock *MBB,
95 bool isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
99 bool PerformTrivialForwardCoalescing(MachineInstr *MI,
114 bool MachineSinking::PerformTrivialForwardCoalescing(MachineInstr *MI, argument
116 if (!MI->isCopy())
119 unsigned SrcReg = MI->getOperand(1).getReg();
120 unsigned DstReg = MI
258 MachineInstr *MI = I; // The instruction to sink. local
284 isWorthBreakingCriticalEdge(MachineInstr *MI, MachineBasicBlock *From, MachineBasicBlock *To) argument
331 SplitCriticalEdge(MachineInstr *MI, MachineBasicBlock *FromBB, MachineBasicBlock *ToBB, bool BreakPHIEdge) argument
399 AvoidsSinking(MachineInstr *MI, MachineRegisterInfo *MRI) argument
405 collectDebugValues(MachineInstr *MI, SmallVectorImpl<MachineInstr *> &DbgValues) argument
440 isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, MachineBasicBlock *MBB, MachineBasicBlock *SuccToSinkTo) argument
476 FindSuccToSinkTo(MachineInstr *MI, MachineBasicBlock *MBB, bool &BreakPHIEdge) argument
588 SinkInstruction(MachineInstr *MI, bool &SawStore) argument
[all...]
H A DTargetInstrInfo.cpp63 MachineBasicBlock::iterator MI) const {
121 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI, argument
123 const MCInstrDesc &MCID = MI->getDesc();
125 if (HasDef && !MI->getOperand(0).isReg())
129 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
130 assert(MI->isCommutable() && "Precondition violation: MI must be commutable.");
134 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
136 unsigned Reg0 = HasDef ? MI
180 findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const argument
214 PredicateInstruction(MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Pred) const argument
244 hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const argument
264 hasStoreToStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const argument
320 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); local
341 canFoldCopy(const MachineInstr *MI, unsigned FoldIdx) argument
374 canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops) const argument
379 foldPatchpoint(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, int FrameIndex, const TargetInstrInfo &TII) argument
445 foldMemoryOperand(MachineBasicBlock::iterator MI, const SmallVectorImpl<unsigned> &Ops, int FI) const argument
514 foldMemoryOperand(MachineBasicBlock::iterator MI, const SmallVectorImpl<unsigned> &Ops, MachineInstr* LoadMI) const argument
561 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, AliasAnalysis *AA) const argument
646 isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const argument
765 getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost) const argument
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H A DMachineCSE.cpp81 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
85 bool hasLivePhysRegDefUses(const MachineInstr *MI,
90 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
94 bool isCSECandidate(MachineInstr *MI);
96 MachineInstr *CSMI, MachineInstr *MI);
115 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI, argument
118 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
119 MachineOperand &MO = MI->getOperand(i);
155 DEBUG(dbgs() << "*** to: " << *MI);
209 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI, argument
261 PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI, SmallSet<unsigned,8> &PhysRefs, SmallVectorImpl<unsigned> &PhysDefs, bool &NonLocal) const argument
328 isCSECandidate(MachineInstr *MI) argument
357 isProfitableToCSE(unsigned CSReg, unsigned Reg, MachineInstr *CSMI, MachineInstr *MI) argument
448 MachineInstr *MI = &*I; local
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H A DOptimizePHIs.cpp52 bool IsSingleValuePHICycle(MachineInstr *MI, unsigned &SingleValReg,
54 bool IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle);
82 /// IsSingleValuePHICycle - Check if MI is a PHI where all the source operands
87 bool OptimizePHIs::IsSingleValuePHICycle(MachineInstr *MI, argument
90 assert(MI->isPHI() && "IsSingleValuePHICycle expects a PHI instruction");
91 unsigned DstReg = MI->getOperand(0).getReg();
94 if (!PHIsInCycle.insert(MI))
102 for (unsigned i = 1; i != MI->getNumOperands(); i += 2) {
103 unsigned SrcReg = MI->getOperand(i).getReg();
132 bool OptimizePHIs::IsDeadPHICycle(MachineInstr *MI, InstrSe argument
160 MachineInstr *MI = &*MII++; local
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H A DProcessImplicitDefs.cpp34 void processImplicitDef(MachineInstr *MI);
35 bool canTurnIntoImplicitDef(MachineInstr *MI);
64 bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) { argument
65 if (!MI->isCopyLike() &&
66 !MI->isInsertSubreg() &&
67 !MI->isRegSequence() &&
68 !MI->isPHI())
70 for (MIOperands MO(MI); MO.isValid(); ++MO)
76 void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) { argument
77 DEBUG(dbgs() << "Processing " << *MI);
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/external/llvm/lib/Target/Mips/
H A DMips16ISelLowering.h28 EmitInstrWithCustomInserter(MachineInstr *MI,
51 MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr *MI,
55 MachineInstr *MI,
59 MachineInstr *MI,
63 MachineInstr *MI,
68 MachineInstr *MI, MachineBasicBlock *BB) const;
72 MachineInstr *MI, MachineBasicBlock *BB) const;
76 MachineInstr *MI, MachineBasicBlock *BB )const;
H A DMipsAsmPrinter.h36 void EmitInstrWithMacroNoAT(const MachineInstr *MI);
41 const MachineInstr *MI);
47 const MachineInstr *MI);
112 void EmitInstruction(const MachineInstr *MI) override;
121 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
124 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
127 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
128 void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
129 void printUnsignedImm8(const MachineInstr *MI, int opNum, raw_ostream &O);
130 void printMemOperand(const MachineInstr *MI, in
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/external/llvm/lib/Target/NVPTX/InstPrinter/
H A DNVPTXInstPrinter.h31 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot) override;
34 void printInstruction(const MCInst *MI, raw_ostream &O);
38 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39 void printCvtMode(const MCInst *MI, int OpNum, raw_ostream &O,
41 void printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O,
43 void printLdStCode(const MCInst *MI, int OpNum,
45 void printMemOperand(const MCInst *MI, int OpNum,
47 void printProtoIdent(const MCInst *MI, int OpNum,
/external/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp71 const MachineInstr &MI);
73 const MachineInstr &MI);
74 /// \brief tblgen'erated driver function for lowering simple MI->MC
77 const MachineInstr *MI);
79 void EmitInstruction(const MachineInstr *MI) override;
92 MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
93 void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O);
99 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
102 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
106 void PrintDebugValueComment(const MachineInstr *MI, raw_ostrea
209 printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O) argument
265 PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
345 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
359 PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS) argument
379 LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM, const MachineInstr &MI) argument
392 LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM, const MachineInstr &MI) argument
436 EmitInstruction(const MachineInstr *MI) argument
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/external/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp62 void pushStack(MachineInstr *MI);
63 MachineInstr *getAccDefMI(MachineInstr *MI) const;
64 unsigned getDefReg(MachineInstr *MI) const;
65 bool hasLoopHazard(MachineInstr *MI) const;
66 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
67 bool FindMLxHazard(MachineInstr *MI);
68 void ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI,
81 void MLxExpansion::pushStack(MachineInstr *MI) { argument
82 LastMIs[MIIdx] = MI;
87 MachineInstr *MLxExpansion::getAccDefMI(MachineInstr *MI) cons
213 FindMLxHazard(MachineInstr *MI) argument
272 ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned MulOpc, unsigned AddSubOpc, bool NegAcc, bool HasLane) argument
337 MachineInstr *MI = &*MII; local
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H A DThumb2SizeReduction.cpp152 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
156 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
159 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
164 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
170 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
174 /// ReduceMI - Attempt to reduce MI, return true on success.
175 bool ReduceMI(MachineBasicBlock &MBB, MachineInstr *MI,
291 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry, argument
321 if (!HasImplicitCPSRDef(MI->getDesc()))
333 static bool VerifyLowRegs(MachineInstr *MI) { argument
365 ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, const ReduceEntry &Entry) argument
526 ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI, const ReduceEntry &Entry, bool LiveCPSR, bool IsSelfLoop) argument
628 ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI, const ReduceEntry &Entry, bool LiveCPSR, bool IsSelfLoop) argument
746 ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI, const ReduceEntry &Entry, bool LiveCPSR, bool IsSelfLoop) argument
857 UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR) argument
873 UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) argument
889 ReduceMI(MachineBasicBlock &MBB, MachineInstr *MI, bool LiveCPSR, bool IsSelfLoop) argument
945 MachineInstr *MI = &*MII; local
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/external/llvm/lib/Target/R600/InstPrinter/
H A DAMDGPUInstPrinter.cpp20 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, argument
23 printInstruction(MI, OS);
28 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo, argument
30 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
33 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, argument
35 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
38 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo, argument
40 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
135 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument
138 const MCOperand &Op = MI
161 printOperandAndMods(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
173 printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
188 printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
195 printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef Asm, StringRef Default) argument
207 printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
212 printClamp(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
217 printLiteral(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
223 printLast(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
228 printNeg(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
233 printOMOD(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
249 printRel(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
254 printUpdateExecMask(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
259 printUpdatePred(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
264 printWrite(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
272 printSel(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
296 printBankSwizzle(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
321 printRSel(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
351 printCT(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
366 printKCache(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
378 printSendMsg(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
409 printWaitFlag(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
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/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBundle.h1 //===-- CodeGen/MachineInstBundle.h - MI bundle utilities -------*- C++ -*-===//
44 /// getBundleStart - Returns the first instruction in the bundle containing MI.
46 inline MachineInstr *getBundleStart(MachineInstr *MI) { argument
47 MachineBasicBlock::instr_iterator I = MI;
53 inline const MachineInstr *getBundleStart(const MachineInstr *MI) { argument
54 MachineBasicBlock::const_instr_iterator I = MI;
60 /// Return an iterator pointing beyond the bundle containing MI.
62 getBundleEnd(MachineInstr *MI) { argument
63 MachineBasicBlock::instr_iterator I = MI;
69 /// Return an iterator pointing beyond the bundle containing MI
71 getBundleEnd(const MachineInstr *MI) argument
117 MachineOperandIteratorBase(MachineInstr *MI, bool WholeBundle) argument
214 MIOperands(MachineInstr *MI) argument
223 ConstMIOperands(const MachineInstr *MI) argument
234 MIBundleOperands(MachineInstr *MI) argument
244 ConstMIBundleOperands(const MachineInstr *MI) argument
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/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h70 bool isTriviallyReMaterializable(const MachineInstr *MI, argument
72 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
73 (MI->getDesc().isRematerializable() &&
74 (isReallyTriviallyReMaterializable(MI, AA) ||
75 isReallyTriviallyReMaterializableGeneric(MI, AA)));
85 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, argument
96 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
115 virtual bool isCoalescableExtInstr(const MachineInstr &MI, argument
126 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, argument
134 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, argument
155 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const argument
163 isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const argument
181 isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, int &SrcFrameIndex) const argument
338 getUnconditionalBranch(MCInst &MI, const MCSymbolRefExpr *BranchTarget) const argument
479 analyzeSelect(const MachineInstr *MI, SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const argument
500 optimizeSelect(MachineInstr *MI, bool PreferFalse = false) const argument
514 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
526 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
539 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
579 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI, const SmallVectorImpl<unsigned> &Ops, int FrameIndex) const argument
589 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI, const SmallVectorImpl<unsigned> &Ops, MachineInstr* LoadMI) const argument
606 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
722 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument
781 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
804 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const argument
905 verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const argument
938 setExecutionDomain(MachineInstr *MI, unsigned Domain) const argument
981 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const argument
1001 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const argument
1025 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp135 MachineInstr *MI = MII; local
138 if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) {
139 assert (MI->getNumOperands() == 2);
140 MachineOperand &Dst = MI->getOperand(0);
141 MachineOperand &Src = MI->getOperand(1);
157 MI->getOpcode () == Hexagon::COMBINE_Ir_V4) {
158 assert (MI->getNumOperands() == 3);
159 MachineOperand &Dst = MI->getOperand(0);
160 MachineOperand &Src1 = MI->getOperand(1);
161 MachineOperand &Src2 = MI
[all...]
H A DHexagonExpandPredSpillCode.cpp84 MachineInstr *MI = MII; local
85 int Opc = MI->getOpcode();
88 unsigned FP = MI->getOperand(0).getReg();
91 assert(MI->getOperand(1).isImm() && "Not an offset");
92 int Offset = MI->getOperand(1).getImm();
93 int SrcReg = MI->getOperand(2).getReg();
98 BuildMI(*MBB, MII, MI->getDebugLoc(),
101 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
106 BuildMI(*MBB, MII, MI
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/external/llvm/lib/Target/R600/
H A DSIFixSGPRCopies.cpp117 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) { argument
118 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
119 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
120 if (!MI.getOperand(i).isReg() ||
121 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg()))
124 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
208 MachineInstr &MI = *I; local
209 if (MI.getOpcode() == AMDGPU::COPY && isVGPRToSGPRCopy(MI, TRI, MRI)) {
211 DEBUG(MI
[all...]
/external/llvm/lib/Target/SystemZ/
H A DSystemZLongBranch.cpp147 TerminatorInfo describeTerminator(MachineInstr *MI);
152 void splitBranchOnCount(MachineInstr *MI, unsigned AddOpcode);
153 void splitCompareBranch(MachineInstr *MI, unsigned CompareOpcode);
209 // Return a description of terminator instruction MI.
210 TerminatorInfo SystemZLongBranch::describeTerminator(MachineInstr *MI) { argument
212 Terminator.Size = TII->getInstSizeInBytes(MI);
213 if (MI->isConditionalBranch() || MI->isUnconditionalBranch()) {
214 switch (MI->getOpcode()) {
251 Terminator.Branch = MI;
280 MachineBasicBlock::iterator MI = MBB->begin(); local
347 splitBranchOnCount(MachineInstr *MI, unsigned AddOpcode) argument
366 splitCompareBranch(MachineInstr *MI, unsigned CompareOpcode) argument
[all...]
H A DSystemZElimCompare.cpp77 Reference getRegReferences(MachineInstr *MI, unsigned Reg);
78 bool convertToBRCT(MachineInstr *MI, MachineInstr *Compare,
80 bool convertToLoadAndTest(MachineInstr *MI);
81 bool adjustCCMasksForInstr(MachineInstr *MI, MachineInstr *Compare,
107 // Return true if any CC result of MI would reflect the value of subreg
109 static bool resultTests(MachineInstr *MI, unsigned Reg, unsigned SubReg) { argument
110 if (MI->getNumOperands() > 0 &&
111 MI->getOperand(0).isReg() &&
112 MI->getOperand(0).isDef() &&
113 MI
139 getRegReferences(MachineInstr *MI, unsigned Reg) argument
165 convertToBRCT(MachineInstr *MI, MachineInstr *Compare, SmallVectorImpl<MachineInstr *> &CCUsers) argument
214 convertToLoadAndTest(MachineInstr *MI) argument
231 adjustCCMasksForInstr(MachineInstr *MI, MachineInstr *Compare, SmallVectorImpl<MachineInstr *> &CCUsers) argument
254 MachineInstr *MI = CCUsers[I]; local
336 MachineInstr *MI = MBBI; local
436 MachineInstr *MI = --MBBI; local
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600InstrInfo.h44 MachineBasicBlock::iterator MI, DebugLoc DL,
48 bool isTrig(const MachineInstr &MI) const;
55 bool isVector(const MachineInstr &MI) const;
75 bool isPredicated(const MachineInstr *MI) const;
77 bool isPredicable(MachineInstr *MI) const;
94 bool DefinesPredicate(MachineInstr *MI,
103 bool PredicateInstruction(MachineInstr *MI,
107 const MachineInstr *MI,
115 bool hasFlagOperand(const MachineInstr &MI) const;
118 void addFlag(MachineInstr *MI, unsigne
[all...]
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600InstrInfo.h44 MachineBasicBlock::iterator MI, DebugLoc DL,
48 bool isTrig(const MachineInstr &MI) const;
55 bool isVector(const MachineInstr &MI) const;
75 bool isPredicated(const MachineInstr *MI) const;
77 bool isPredicable(MachineInstr *MI) const;
94 bool DefinesPredicate(MachineInstr *MI,
103 bool PredicateInstruction(MachineInstr *MI,
107 const MachineInstr *MI,
115 bool hasFlagOperand(const MachineInstr &MI) const;
118 void addFlag(MachineInstr *MI, unsigne
[all...]
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.h53 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
59 uint64_t getBinaryCodeForInstr(const MCInst &MI,
66 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
73 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
80 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
87 unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
94 unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
101 unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
108 unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
114 unsigned getMachineOpValue(const MCInst &MI, cons
[all...]
/external/llvm/lib/CodeGen/AsmPrinter/
H A DDbgValueHistoryCalculator.cpp24 // \brief If @MI is a DBG_VALUE with debug value described by a
27 static unsigned isDescribedByReg(const MachineInstr &MI) { argument
28 assert(MI.isDebugValue());
29 assert(MI.getNumOperands() == 3);
32 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : 0;
36 const MachineInstr &MI) {
39 assert(MI.isDebugValue() && MI.getDebugVariable() == Var);
42 Ranges.back().first->isIdenticalTo(&MI)) {
35 startInstrRange(const MDNode *Var, const MachineInstr &MI) argument
44 << "\\t" << Ranges.back().first << "\\t" << MI << "\\n"); local
50 endInstrRange(const MDNode *Var, const MachineInstr &MI) argument
115 collectClobberedRegisters(const MachineInstr &MI, const TargetRegisterInfo *TRI, std::set<unsigned> &Regs) argument
[all...]
/external/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.h38 * virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
40 * virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
55 virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
57 bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
58 bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
59 bool isReadSpecialReg(MachineInstr &MI) const;
61 virtual bool CanTailMerge(const MachineInstr *MI) const;
70 unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const {
71 return MI.getOperand(2).getImm();

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