Searched refs:MBB (Results 126 - 150 of 306) sorted by relevance

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/external/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp62 MachineBasicBlock &MBB = *MI->getParent(); local
63 MachineFunction &MF = *MBB.getParent();
108 TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
116 BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
121 TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
122 BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
H A DSystemZInstrInfo.h128 void emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
143 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
147 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
148 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
158 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
169 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
172 void storeRegToStackSlot(MachineBasicBlock &MBB,
177 void loadRegFromStackSlot(MachineBasicBlock &MBB,
237 void loadImmediate(MachineBasicBlock &MBB,
/external/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp100 void UpdateBaseRegUses(MachineBasicBlock &MBB,
104 bool MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
110 void MergeOpsUpdate(MachineBasicBlock &MBB,
124 void MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
129 void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
130 bool FixInvalidRegPairOp(MachineBasicBlock &MBB,
132 bool MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
137 bool MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
141 bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
142 bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
332 UpdateBaseRegUses(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc dl, unsigned Base, unsigned WordOffset, ARMCC::CondCodes Pred, unsigned PredReg) argument
413 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument
610 MergeOpsUpdate(MachineBasicBlock &MBB, MemOpQueue &memOps, unsigned memOpsBegin, unsigned memOpsEnd, unsigned insertAfter, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, SmallVectorImpl<MachineBasicBlock::iterator> &Merges) argument
708 MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base, int Opcode, unsigned Size, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, MemOpQueue &MemOps, SmallVectorImpl<MachineBasicBlock::iterator> &Merges) argument
983 MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool &Advance, MachineBasicBlock::iterator &I) argument
1121 MergeBaseUpdateLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const TargetInstrInfo *TII, bool &Advance, MachineBasicBlock::iterator &I) argument
1316 AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps) argument
1358 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument
1382 FixInvalidRegPairOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) argument
1504 LoadStoreMultipleOpti(MachineBasicBlock &MBB) argument
1695 MergeReturnIntoLDM(MachineBasicBlock &MBB) argument
1746 MachineBasicBlock &MBB = *MFI; local
1948 RescheduleOps(MachineBasicBlock *MBB, SmallVectorImpl<MachineInstr *> &Ops, unsigned Base, bool isLd, DenseMap<MachineInstr*, unsigned> &MI2LocMap) argument
2108 RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) argument
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/external/llvm/include/llvm/CodeGen/
H A DDFAPacketizer.h117 void PacketizeMIs(MachineBasicBlock *MBB,
133 void endPacket(MachineBasicBlock *MBB, MachineInstr *MI);
142 MachineBasicBlock *MBB) {
141 ignorePseudoInstruction(MachineInstr *I, MachineBasicBlock *MBB) argument
H A DMachineFunction.h60 void addNodeToList(MachineBasicBlock* MBB);
61 void removeNodeFromList(MachineBasicBlock* MBB);
62 void deleteNode(MachineBasicBlock *MBB);
100 // numbered and this vector keeps track of the mapping from ID's to MBB's.
253 /// basic block can be found by using the MBB::getBlockNumber method, this
265 /// getNumBlockIDs - Return the number of MBB ID's allocated.
270 /// recomputes them. This guarantees that the MBB numbers are sequential,
334 void push_back (MachineBasicBlock *MBB) { BasicBlocks.push_back (MBB); }
335 void push_front(MachineBasicBlock *MBB) { BasicBlock
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/external/llvm/lib/CodeGen/
H A DLiveRangeCalc.h59 /// For every basic block, MBB, one of these conditions shall be true:
61 /// 1. !Seen.count(MBB->getNumber())
63 /// 2. LiveOut[MBB].second.getNode() == MBB
64 /// The live-out value is defined in MBB.
65 /// 3. forall P in preds(MBB): LiveOut[P] == LiveOut[MBB]
66 /// The live-out value passses through MBB. All predecessors must carry
199 /// setLiveOutValue - Indicate that VNI is live out from MBB. The
200 /// calculateValues() function will not add liveness for MBB, th
205 setLiveOutValue(MachineBasicBlock *MBB, VNInfo *VNI) argument
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H A DLiveDebugVariables.cpp90 bool dominates(MachineBasicBlock *MBB) { argument
93 if (LBlocks.count(MBB) != 0 || LS.dominates(DL, MBB))
131 /// insertDebugValue - Insert a DBG_VALUE into MBB at Idx for LocNo.
132 void insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, unsigned LocNo,
477 MachineBasicBlock *MBB = MFI; local
478 for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
485 SlotIndex Idx = MBBI == MBB->begin() ?
486 LIS->getMBBStartIdx(MBB)
510 MachineBasicBlock *MBB = LIS.getMBBFromIndex(Start); local
555 MachineBasicBlock *MBB = Children[i]->getBlock(); local
903 findInsertLocation(MachineBasicBlock *MBB, SlotIndex Idx, LiveIntervals &LIS) argument
929 insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, unsigned LocNo, LiveIntervals &LIS, const TargetInstrInfo &TII) argument
954 MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start); local
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/external/llvm/lib/Target/R600/
H A DSIFixSGPRLiveRanges.cpp83 MachineBasicBlock &MBB = *BI; local
84 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
H A DAMDGPUFrameLowering.h41 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
H A DR600InstrInfo.cpp49 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, argument
69 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
76 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
84 bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB, argument
674 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
676 while (I != MBB.begin()) {
697 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
705 MachineBasicBlock::iterator I = MBB.end();
706 if (I == MBB.begin())
710 if (I == MBB
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDILFrameLowering.cpp46 AMDGPUFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
H A DSIInstrInfo.h33 virtual void copyPhysReg(MachineBasicBlock &MBB,
H A DAMDGPUMCInstLower.cpp67 const MachineBasicBlock *MBB = MI->getParent(); local
70 while (I != MBB->end() && I->isInsideBundle()) {
H A DSIInstrInfo.cpp37 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, argument
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
/external/llvm/include/llvm/Target/
H A DTargetFrameLowering.h135 MachineBasicBlock &MBB) const = 0;
149 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, argument
160 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, argument
228 MachineBasicBlock &MBB,
227 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const argument
/external/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h62 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
67 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
69 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
78 void copyPhysReg(MachineBasicBlock &MBB,
83 void storeRegToStackSlot(MachineBasicBlock &MBB,
94 void loadRegFromStackSlot(MachineBasicBlock &MBB,
124 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
148 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
156 const MachineBasicBlock *MBB,
/external/llvm/lib/Target/Mips/
H A DMips16RegisterInfo.h32 bool saveScavengerRegister(MachineBasicBlock &MBB,
H A DMipsConstantIslandPass.cpp393 void computeBlockSize(MachineBasicBlock *MBB);
603 static bool BBHasFallthrough(MachineBasicBlock *MBB) { argument
605 MachineFunction::iterator MBBI = MBB;
607 if (std::next(MBBI) == MBB->getParent()->end())
611 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
612 E = MBB->succ_end(); I != E; ++I)
672 MachineBasicBlock &MBB = *MBBI; local
674 // If this block doesn't fall through into the next MBB, then this is
676 if (!BBHasFallthrough(&MBB))
677 WaterList.push_back(&MBB);
816 computeBlockSize(MachineBasicBlock *MBB) argument
830 MachineBasicBlock *MBB = MI->getParent(); local
1034 BBIsJumpedOver(MachineBasicBlock *MBB) argument
1547 MachineBasicBlock *MBB = MI->getParent(); local
1612 MachineBasicBlock *MBB = MI->getParent(); local
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/external/llvm/lib/Target/Sparc/
H A DSparcCodeEmitter.cpp68 MachineBasicBlock &MBB);
116 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
117 MBB != E; ++MBB){
118 MCE.StartMachineBasicBlock(MBB);
119 for (MachineBasicBlock::instr_iterator I = MBB->instr_begin(),
120 E = MBB->instr_end(); I != E;)
121 emitInstruction(*I++, *MBB);
129 MachineBasicBlock &MBB) {
128 emitInstruction(MachineBasicBlock::instr_iterator MI, MachineBasicBlock &MBB) argument
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILFrameLowering.cpp46 AMDGPUFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
H A DSIInstrInfo.h33 virtual void copyPhysReg(MachineBasicBlock &MBB,
/external/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp109 MachineFunction &MF, MachineBasicBlock &MBB,
142 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, Amount, TII);
148 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, -CalleePopAmount,
151 MBB.erase(I);
155 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
157 MachineFunction &MF = *MBB.getParent();
162 DebugLoc DL = MBB.findDebugLoc(MBBI);
197 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
203 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB. local
204 MachineBasicBlock::iterator MBBI = MBB
108 eliminateCallFramePseudoInstr( MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
615 spillCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
691 restoreCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
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H A DAArch64ConditionalCompares.cpp182 /// Find the compare instruction in MBB that controls the conditional branch.
184 MachineInstr *findConvertibleCompare(MachineBasicBlock *MBB);
186 /// Return true if all non-terminator instructions in MBB can be safely
188 bool canSpeculateInstrs(MachineBasicBlock *MBB, const MachineInstr *CmpMI);
199 /// If the sub-CFG headed by MBB can be cmp-converted, initialize the
201 bool canConvert(MachineBasicBlock *MBB);
220 // PHI operands come in (VReg, MBB) pairs.
222 MachineBasicBlock *MBB = I.getOperand(oi + 1).getMBB(); local
224 if (MBB == Head) {
228 if (MBB
298 findConvertibleCompare(MachineBasicBlock *MBB) argument
380 canSpeculateInstrs(MachineBasicBlock *MBB, const MachineInstr *CmpMI) argument
436 canConvert(MachineBasicBlock *MBB) argument
878 tryConvert(MachineBasicBlock *MBB) argument
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H A DAArch64InstrInfo.cpp38 const MachineBasicBlock &MBB = *MI->getParent(); local
39 const MachineFunction *MF = MBB.getParent();
92 bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, argument
98 MachineBasicBlock::iterator I = MBB.end();
99 if (I == MBB.begin())
103 if (I == MBB.begin())
115 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
139 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
151 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
225 unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) cons
255 instantiateCondBranch( MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB, const SmallVectorImpl<MachineOperand> &Cond) const argument
271 InsertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
369 canInsertSelect( const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
410 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DstReg, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg) const argument
662 MachineBasicBlock *MBB = Instr->getParent(); local
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp83 // Instructions are appended to FuncInfo.MBB. If the basic block already
87 if (!FuncInfo.MBB->empty())
88 EmitStartPt = &FuncInfo.MBB->back();
236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
317 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
320 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
323 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
350 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
645 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
649 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInf
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