Searched defs:Op (Results 176 - 200 of 272) sorted by relevance

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/external/llvm/lib/Analysis/
H A DScalarEvolution.cpp145 const SCEV *Op = Trunc->getOperand(); local
146 OS << "(trunc " << *Op->getType() << " " << *Op << " to "
152 const SCEV *Op = ZExt->getOperand(); local
153 OS << "(zext " << *Op->getType() << " " << *Op << " to "
159 const SCEV *Op = SExt->getOperand(); local
160 OS << "(sext " << *Op->getType() << " " << *Op << " to "
335 : SCEV(ID, SCEVTy), Op(o
821 getTruncateExpr(const SCEV *Op, Type *Ty) argument
900 getZeroExtendExpr(const SCEV *Op, Type *Ty) argument
1157 getSignExtendExpr(const SCEV *Op, Type *Ty) argument
1342 getAnyExtendExpr(const SCEV *Op, Type *Ty) argument
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H A DScalarEvolutionExpander.cpp35 Instruction::CastOps Op,
54 if (CI->getOpcode() == Op) {
62 Ret = CastInst::Create(Op, V, Ty, "", IP);
74 Ret = CastInst::Create(Op, V, Ty, V->getName(), IP);
89 Instruction::CastOps Op = CastInst::getCastOpcode(V, false, Ty, false); local
90 assert((Op == Instruction::BitCast ||
91 Op == Instruction::PtrToInt ||
92 Op == Instruction::IntToPtr) &&
98 if (Op == Instruction::BitCast) {
107 if ((Op
34 ReuseOrCreateCast(Value *V, Type *Ty, Instruction::CastOps Op, BasicBlock::iterator IP) argument
423 const SCEV *Op = Ops[i]; local
724 const SCEV *Op = I->second; local
791 const SCEV *Op = I->second; local
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/external/llvm/lib/Bitcode/Reader/
H A DBitcodeReader.cpp242 : ConstantExpr(Ty, Instruction::UserOp1, &Op<0>(), 1) {
243 Op<0>() = UndefValue::get(Type::getInt32Ty(Context));
1400 Constant *Op = ValueList.getConstantFwdRef(Record[2], OpTy);
1401 V = UpgradeBitCastExpr(Opc, Op, CurTy);
1402 if (!V) V = ConstantExpr::getCast(Opc, Op, CurTy);
2411 Value *Op; local
2412 if (getValueTypePair(Record, OpNum, NextValueNo, Op) ||
2421 if ((I = UpgradeBitCastInst(Opc, Op, ResTy, Temp))) {
2427 I = CastInst::Create((Instruction::CastOps)Opc, Op, ResTy);
2441 Value *Op; local
2611 Value *Op = nullptr; local
2790 Value *Op; local
2901 Value *Op; local
2913 Value *Op; local
3080 Value *Op; local
3104 Value *Op = getValue(Record, 1, NextValueNo, OpTy); local
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/external/llvm/lib/Bitcode/Writer/
H A DBitcodeWriter.cpp109 static unsigned GetEncodedRMWOperation(AtomicRMWInst::BinOp Op) { argument
110 switch (Op) {
/external/llvm/lib/CodeGen/
H A DIfConversion.cpp990 MachineOperand &Op = *Ops; local
991 MachineInstr *MI = Op.getParent();
H A DMachineInstr.cpp610 void MachineInstr::addOperand(const MachineOperand &Op) { argument
615 addOperand(*MF, Op);
639 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) { argument
643 if (&Op >= Operands && &Op < Operands + NumOperands) {
645 // If adding Op requires reallocating or moving existing operands around,
646 // the Op reference could go stale. Support it by copying Op.
647 MachineOperand CopyOp(Op);
659 bool isImpReg = Op
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp228 } else if (const Operator *Op = dyn_cast<Operator>(V)) {
229 if (!SelectOperator(Op, Op->getOpcode()))
230 if (!isa<Instruction>(Op) ||
231 !TargetSelectInstruction(cast<Instruction>(Op)))
233 Reg = lookUpRegForValue(Op);
721 Optional<MachineOperand> Op; local
726 Op = MachineOperand::CreateFI(Offset);
727 if (!Op)
729 Op
1326 constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, unsigned OpNum) argument
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H A DScheduleDAGRRList.cpp956 const SDValue &Op = N->getOperand(i); local
957 EVT VT = Op.getNode()->getValueType(Op.getResNo());
1246 if (const RegisterMaskSDNode *Op =
1248 return Op->getRegMask();
1726 bool canClobber(const SUnit *SU, const SUnit *Op);
2682 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) {
2692 Op->OrigNode == &(*SUnits)[DU->getNodeId()])
H A DSelectionDAGISel.cpp1860 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) { argument
1861 SDLoc dl(Op);
1862 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0));
1865 RegStr->getString().data(), Op->getValueType(0));
1867 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0));
1873 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) { argument
1874 SDLoc dl(Op);
1875 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1878 RegStr->getString().data(), Op->getOperand(2).getValueType());
1880 CurDAG->getEntryNode(), dl, Reg, Op
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/external/llvm/lib/IR/
H A DAsmWriter.cpp656 if (const MDNode *Op = dyn_cast_or_null<MDNode>(N->getOperand(i)))
657 CreateMetadataSlot(Op);
715 AtomicRMWInst::BinOp Op) {
716 switch (Op) {
717 default: Out << " <unknown operation " << Op << ">"; break; local
2116 Value *Op = Node->getOperand(0);
2117 if (!Op || !isa<ConstantInt>(Op) || cast<ConstantInt>(Op)->getBitWidth() < 32)
714 writeAtomicRMWOperation(raw_ostream &Out, AtomicRMWInst::BinOp Op) argument
H A DVerifier.cpp267 void visitModuleFlag(const MDNode *Op,
571 Value *Op = MD.getOperand(i); local
572 if (!Op)
574 if (isa<Constant>(Op) || isa<MDString>(Op))
576 if (MDNode *N = dyn_cast<MDNode>(Op)) {
582 Assert2(MD.isFunctionLocal(), "Invalid operand for global metadata!", &MD, Op);
587 if (Instruction *I = dyn_cast<Instruction>(Op))
589 else if (BasicBlock *BB = dyn_cast<BasicBlock>(Op))
591 else if (Argument *A = dyn_cast<Argument>(Op))
651 const MDNode *Op = SeenIDs.lookup(Flag); local
668 visitModuleFlag(const MDNode *Op, DenseMap<const MDString *, const MDNode *> &SeenIDs, SmallVectorImpl<const MDNode *> &Requirements) argument
2142 Instruction *Op = cast<Instruction>(I.getOperand(i)); local
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/external/llvm/lib/Linker/
H A DLinkModules.cpp1259 MDNode *Op = DstModFlags->getOperand(I); local
1260 ConstantInt *Behavior = cast<ConstantInt>(Op->getOperand(0));
1261 MDString *ID = cast<MDString>(Op->getOperand(1));
1264 Requirements.insert(cast<MDNode>(Op->getOperand(2)));
1266 Flags[ID] = Op;
1383 MDNode *Op = Flags[Flag]; local
1384 if (!Op || Op->getOperand(2) != ReqValue) {
/external/llvm/lib/TableGen/
H A DRecord.cpp1601 Init *Op = Val->resolveReferences(R, RV); local
1603 if (Args != NewArgs || Op != Val)
1604 return DagInit::get(Op, ValName, NewArgs, ArgNames);
/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp356 const Value *Op = *i; local
359 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
364 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
369 if (canFoldAddIntoGEP(U, Op)) {
372 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
375 Op = cast<AddOperator>(Op)->getOperand(0);
1090 unsigned Op = getRegForValue(V); local
1091 if (Op == 0)
1096 ResultReg).addReg(Op);
1106 unsigned Op = getRegForValue(V); local
1647 Value *Op = I->getOperand(0); local
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H A DAArch64ISelDAGToDAG.cpp69 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
216 const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
221 OutOps.push_back(Op);
1588 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth = 0);
1590 static void getUsefulBitsFromAndWithImmediate(SDValue Op, APInt &UsefulBits, argument
1593 cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
1596 getUsefulBits(Op, UsefulBits, Depth + 1);
1599 static void getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits, argument
1610 getUsefulBits(Op, OpUsefulBits, Depth + 1);
1618 getUsefulBits(Op, OpUsefulBit
215 SelectInlineAsmMemoryOperand( const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) argument
1626 getUsefulBitsFromUBFM(SDValue Op, APInt &UsefulBits, unsigned Depth) argument
1636 getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits, unsigned Depth) argument
1664 getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits, unsigned Depth) argument
1724 getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth) argument
1751 getLeftShift(SelectionDAG *CurDAG, SDValue Op, int ShlAmount) argument
1780 isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op, SDValue &Src, int &ShiftAmount, int &MaskWidth) argument
2162 unsigned Op = local
2179 unsigned Op = local
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/external/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp1977 MachineInstr *Op = Ops[i]; local
1978 unsigned Loc = MI2LocMap[Op];
1981 FirstOp = Op;
1985 LastOp = Op;
1989 = getLoadStoreMultipleOpcode(Op->getOpcode(), ARM_AM::ia);
1993 int Offset = getMemoryOpOffset(Op);
1994 unsigned Bytes = getLSMultipleTransferSize(Op);
2092 MachineInstr *Op = Ops.back(); local
2094 MBB->splice(InsertPos, MBB, Op);
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp88 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
91 bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset);
1567 bool HexagonDAGToDAGISel::SelectAddr(SDNode *Op, SDValue Addr, argument
1592 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, argument
1601 if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
H A DHexagonISelLowering.cpp289 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) argument
653 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, argument
676 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
688 SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op, argument
690 SDNode *Node = Op.getNode();
738 return Op;
746 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const argument
748 SDValue Chain = Op.getOperand(0);
749 SDValue Table = Op.getOperand(1);
750 SDValue Index = Op
783 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const argument
938 LowerVASTART(SDValue Op, SelectionDAG &DAG) const argument
951 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const argument
966 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const argument
992 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const argument
1010 LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const argument
1017 LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const argument
1035 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const argument
1519 LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const argument
1546 LowerOperation(SDValue Op, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp199 Constant *Op = CE->getOperand(0); local
200 Op = ConstantExpr::getIntegerCast(Op, TD.getIntPtrType(CV->getContext()),
202 return LowerConstant(Op, AP);
209 Constant *Op = CE->getOperand(0); local
212 const MCExpr *OpExpr = LowerConstant(Op, AP);
216 if (TD.getTypeAllocSize(Ty) == TD.getTypeAllocSize(Op->getType()))
222 unsigned InBits = TD.getTypeAllocSizeInBits(Op->getType());
/external/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp283 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
551 auto Op = make_unique<PPCOperand>(Token); local
552 Op->Tok.Data = Str.data();
553 Op->Tok.Length = Str.size();
554 Op->StartLoc = S;
555 Op->EndLoc = S;
556 Op->IsPPC64 = IsPPC64;
557 return Op;
568 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
569 Op
580 auto Op = make_unique<PPCOperand>(Immediate); local
590 auto Op = make_unique<PPCOperand>(Expression); local
601 auto Op = make_unique<PPCOperand>(TLSRegister); local
1564 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp); local
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/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp324 const Value *Op = *II; local
327 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
332 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
337 if (canFoldAddIntoGEP(U, Op)) {
340 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
343 Op = cast<AddOperator>(Op)->getOperand(0);
H A DPPCISelDAGToDAG.cpp174 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
177 OutOps.push_back(Op);
306 static bool isIntS16Immediate(SDValue Op, short &Imm) { argument
307 return isIntS16Immediate(Op.getNode(), Imm);
757 SDValue Op = N->getOperand(0); local
761 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
762 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
769 Op, getI32Imm(~0U)), 0);
770 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
786 SDValue Op = N->getOperand(0); local
1041 SDNode *Op = local
1047 SDNode *Op = local
1669 SDValue Op = MachineNode->getOperand(1); local
1687 SDValue Op = MachineNode->getOperand(0); local
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/external/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp567 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { argument
570 switch (Op.getOpcode()) {
571 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
572 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
573 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
574 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
576 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
578 case ISD::FSIN: return LowerTrig(Op, DAG);
579 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
580 case ISD::STORE: return LowerSTORE(Op, DA
845 SDValue Op = SDValue(N, 0); local
854 SDValue Op = SDValue(N, 0); local
863 SDValue Op = SDValue(N, 0); local
872 SDValue Op = SDValue(N, 0); local
881 SDValue Op = SDValue(N, 1); local
888 SDValue Op = SDValue(N, 0); local
979 LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const argument
995 LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const argument
1012 LowerTrig(SDValue Op, SelectionDAG &DAG) const argument
1043 LowerSHLParts(SDValue Op, SelectionDAG &DAG) const argument
1079 LowerSRXParts(SDValue Op, SelectionDAG &DAG) const argument
1117 LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const argument
1153 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const argument
1343 LowerSTORE(SDValue Op, SelectionDAG &DAG) const argument
1497 LowerLOAD(SDValue Op, SelectionDAG &DAG) const argument
1646 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const argument
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H A DSIISelLowering.cpp183 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
184 switch(Op) {
196 setOperationAction(Op, VT, Expand);
600 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { argument
603 switch (Op.getOpcode()) {
604 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
605 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
607 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
841 LowerLOAD(SDValue Op, SelectionDAG &DAG) const argument
893 LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op, SelectionDAG &DAG) const argument
902 LowerSELECT(SDValue Op, SelectionDAG &DAG) const argument
929 LowerSTORE(SDValue Op, SelectionDAG &DAG) const argument
1235 const SDValue &Op = Mov->getOperand(0); local
1316 fitsRegClass(SelectionDAG &DAG, const SDValue &Op, unsigned RegClass) const argument
1623 SDValue Op = DAG.getTargetConstant(Idx, MVT::i32); local
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H A DSIInstrInfo.cpp275 static unsigned getNumSubRegsForSpillOp(unsigned Op) { argument
277 switch (Op) {
807 MachineOperand &Op,
811 if (Op.isImm()) {
814 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
816 return MachineOperand::CreateImm(Op.getImm() >> 32);
821 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
830 const MachineOperand &Op) const {
839 .addImm(Op.getImm() & 0xFFFFFFFF);
842 .addImm(Op
804 buildExtractSubRegOrImm( MachineBasicBlock::iterator MII, MachineRegisterInfo &MRI, MachineOperand &Op, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const argument
1262 MachineOperand &Op = Inst->getOperand(i); local
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