/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 48 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, argument 50 const Function *F = DAG.getMachineFunction().getFunction(); 86 TargetLowering::makeLibCall(SelectionDAG &DAG, argument 98 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); 103 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy()); 105 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 106 TargetLowering::CallLoweringInfo CLI(DAG); 107 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) 117 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, argument 201 NewLHS = makeLibCall(DAG, LC 1087 computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument 1120 ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) argument 1209 SelectionDAG &DAG = DCI.DAG; local 2531 ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, const TargetLowering &TLI, SDValue Op, SelectionDAG *DAG) argument 2646 BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector<SDNode *> *Created) const argument 2705 BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector<SDNode *> *Created) const argument 2786 expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL, SDValue LH, SDValue RL, SDValue RH) const argument [all...] |
H A D | LegalizeVectorTypes.cpp | 37 N->dump(&DAG); 45 N->dump(&DAG); 138 return DAG.getNode(N->getOpcode(), SDLoc(N), 146 return DAG.getNode(N->getOpcode(), SDLoc(N), 158 return DAG.getNode(ISD::BITCAST, SDLoc(N), 168 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); 175 return DAG.getConvertRndSat(NewVT, SDLoc(N), 176 Op0, DAG.getValueType(NewVT), 177 DAG.getValueType(Op0.getValueType()), 184 return DAG 2638 FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, unsigned Width, EVT WidenVT, unsigned Align = 0, unsigned WidenEx = 0) argument 2691 BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, SmallVectorImpl<SDValue> &LdOps, unsigned Start, unsigned End) argument [all...] |
H A D | SelectionDAG.cpp | 1037 assert(VT.isVector() && "This DAG node is restricted to vector types."); 1047 assert(VT.isVector() && "This DAG node is restricted to vector types."); 1057 assert(VT.isVector() && "This DAG node is restricted to vector types."); 1128 // only legalize if the DAG tells us we must produce legal types. 3681 static SDValue getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG, argument 3690 return DAG.getConstant(Val, VT); 3691 return DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(VT), Val), VT); 3694 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); 3699 Value = DAG 3708 getMemsetStringVal(EVT VT, SDLoc dl, SelectionDAG &DAG, const TargetLowering &TLI, StringRef Str) argument 3750 getMemBasePlusOffset(SDValue Base, unsigned Offset, SDLoc dl, SelectionDAG &DAG) argument 3780 FindOptimalMemOpLowering(std::vector<EVT> &MemOps, unsigned Limit, uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, bool AllowOverlap, SelectionDAG &DAG, const TargetLowering &TLI) argument 3883 getMemcpyLoadsAndStores(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, unsigned Align, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) argument 4000 getMemmoveLoadsAndStores(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, unsigned Align, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) argument 4097 getMemsetStores(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, unsigned Align, bool isVol, MachinePointerInfo DstPtrInfo) argument 6751 checkForCyclesHelper(const SDNode *N, SmallPtrSet<const SDNode*, 32> &Visited, SmallPtrSet<const SDNode*, 32> &Checked, const llvm::SelectionDAG *DAG) argument 6776 checkForCycles(const llvm::SDNode *N, const llvm::SelectionDAG *DAG, bool force) argument 6793 checkForCycles(const llvm::SelectionDAG *DAG, bool force) argument [all...] |
H A D | DAGCombiner.cpp | 1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11 // both before and after the DAG is legalized. 54 cl::desc("Enable DAG combiner alias-analysis heuristics")); 58 cl::desc("Enable DAG combiner's use of IR alias analysis")); 62 cl::desc("Enable DAG combiner's use of TBAA")); 67 cl::desc("Only use DAG-combiner alias analysis in this" 82 SelectionDAG &DAG; member in class:__anon25798::DAGCombiner 110 // AA - Used for DAG load/store alias analysis. 197 /// target-specific DAG combine 512 GetNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOperations, unsigned Depth = 0) argument 1460 combineShlAddConstant(SDLoc DL, SDValue N0, SDValue N1, SelectionDAG &DAG) argument 1715 tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT, SelectionDAG &DAG, bool LegalOperations, bool LegalTypes) argument 4596 SplitVSETCC(const SDNode *N, SelectionDAG &DAG) argument 4614 ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) argument 4800 tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI, SelectionDAG &DAG, bool LegalTypes, bool LegalOperations) argument 5161 isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, APInt &KnownZero) argument 7541 canFoldInAddressingMode(SDNode *N, SDNode *Use, SelectionDAG &DAG, const TargetLowering &TLI) argument 8168 SelectionDAG *DAG; member in struct:__anon25800::LoadedSlice 8693 SelectionDAG &DAG = DC->getDAG(); local 10517 partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) argument [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===// 357 SelectionDAG &DAG) const { 359 case ISD::LOAD: return lowerLOAD(Op, DAG); 360 case ISD::STORE: return lowerSTORE(Op, DAG); 361 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); 362 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); 363 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); 364 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); 365 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); 366 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); 524 performADDECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 544 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 660 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 780 performSUBECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 793 genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG) argument 831 performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL) argument 844 performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget *Subtarget) argument 868 performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 891 performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 938 performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 967 performSETCCCombine(SDNode *N, SelectionDAG &DAG) argument 980 performVSELECTCombine(SDNode *N, SelectionDAG &DAG) argument 1036 performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget *Subtarget) argument 1065 SelectionDAG &DAG = DCI.DAG; local 1099 N->printrWithDepth(dbgs(), &DAG); local 1101 Val.getNode()->printrWithDepth(dbgs(), &DAG); local 1281 initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) argument 1289 extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) argument 1307 lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument 1356 lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument 1369 lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) argument 1398 lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) argument 1402 getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG) argument 1438 lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian) argument 1481 lowerMSABitClear(SDValue Op, SelectionDAG &DAG) argument 1491 lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) argument 2147 lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) argument 2215 lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) argument 2413 lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2471 lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2501 lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2531 lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2561 lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2592 lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2618 lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument 2642 lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument [all...] |
H A D | MipsISelLowering.cpp | 1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 11 // selection DAG. 85 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { argument 86 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 87 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 91 SelectionDAG &DAG, 93 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 97 SelectionDAG &DAG, 99 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 103 SelectionDAG &DAG, 90 getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument 96 getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument 102 getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument 108 getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument 114 getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const argument 428 performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 506 createFPCmp(SelectionDAG &DAG, const SDValue &Op) argument 528 createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, SDLoc DL) argument 538 performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 617 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 657 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 711 performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument 740 SelectionDAG &DAG = DCI.DAG; local 1757 lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert) argument 1803 lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert) argument 1965 lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const argument 2006 createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset) argument 2088 createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset) argument 2105 lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle) argument 2134 lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) argument 2390 SelectionDAG &DAG = CLI.DAG; local 2604 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SDNode *CallNode, const Type *RetTy) const argument 2643 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 3533 copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, const MipsCC &CC, const ByValArgInfo &ByVal) const argument 3577 passByValArg(SDValue Chain, SDLoc DL, std::deque< std::pair<unsigned, SDValue> > &RegsToPass, SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, const MipsCC &CC, const ByValArgInfo &ByVal, const ISD::ArgFlagsTy &Flags, bool isLittle) const argument [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 10 // selection DAG. 255 // We have some custom DAG combine patterns for these nodes 485 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 488 Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy()); 489 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op); 653 SelectionDAG &DAG = CLI.DAG; local 670 MachineFunction &MF = DAG.getMachineFunction(); 675 DAG.getCALLSEQ_START(Chain, DAG 1574 getExtSymb(SelectionDAG &DAG, const char *inname, int idx, EVT v) const argument 1584 getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const argument 1596 getParamHelpSymbol(SelectionDAG &DAG, int idx) argument 1626 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 2661 SelectionDAG &DAG = DCI.DAG; local 3048 ReplaceLoadVector(SDNode *N, SelectionDAG &DAG, SmallVectorImpl<SDValue> &Results) argument 3139 ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG, SmallVectorImpl<SDValue> &Results) argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===// 494 SDLoc DL, SelectionDAG &DAG) const { 495 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); 505 SelectionDAG &DAG = CLI.DAG; local 507 const Function &Fn = *DAG.getMachineFunction().getFunction(); 517 DAG.getContext()->diagnose(NoCalls); 522 SelectionDAG &DAG) const { 529 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); 530 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 1858 isU24(SDValue Op, SelectionDAG &DAG) argument 1866 isI24(SDValue Op, SelectionDAG &DAG) argument 1878 SelectionDAG &DAG = DCI.DAG; local 1890 constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset, uint32_t Width) argument 1933 SelectionDAG &DAG = DCI.DAG; local 2038 getOriginalFunctionArgs( SelectionDAG &DAG, const Function *F, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<ISD::InputArg> &OrigIns) const argument 2090 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument 2165 computeKnownBitsForMinMax(const SDValue Op0, const SDValue Op1, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) argument 2180 computeKnownBitsForTargetNode( const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument 2246 ComputeNumSignBitsForTargetNode( SDValue Op, const SelectionDAG &DAG, unsigned Depth) const argument [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 11 // selection DAG. 175 SDLoc DL, SelectionDAG &DAG) const { 177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 186 SDLoc DL, SelectionDAG &DAG) const { 187 MachineFunction &MF = DAG.getMachineFunction(); 193 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 194 DAG.getTarget(), RVLocs, *DAG 321 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 339 LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 541 LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 660 hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, ImmutableCallSite *CS) argument 685 SelectionDAG &DAG = CLI.DAG; local 971 getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const argument 1711 computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument 1999 LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const argument 2153 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument 2169 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument 2186 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument 2215 LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument 2243 LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument 2264 LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument 2283 LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument 2320 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad) argument 2356 LowerVASTART(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument 2376 LowerVAARG(SDValue Op, SelectionDAG &DAG) argument 2399 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument 2423 getFLUSHW(SDValue Op, SelectionDAG &DAG) argument 2430 getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument 2469 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget) argument 2478 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget) argument 2514 LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode) argument 2543 LowerF128Load(SDValue Op, SelectionDAG &DAG) argument 2594 LowerF128Store(SDValue Op, SelectionDAG &DAG) argument 2637 LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) argument 2669 LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) argument 2720 LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument 2765 LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===// 10 // This file defines a DAG pattern matching instruction selector for X86, 162 return "X86 DAG->DAG Instruction Selection"; 765 // Insert a node into the DAG at least before the Pos node's position. This 768 // IDs! The selection DAG must no longer depend on their uniqueness when this 770 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) { argument 773 DAG.RepositionNode(Pos.getNode(), N.getNode()); 781 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N, argument 797 SDValue Eight = DAG 824 FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 891 FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument [all...] |
H A D | X86InstrInfo.cpp | 4706 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, argument 4720 MachineFunction &MF = DAG.getMachineFunction(); 4756 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl, 4779 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps); 4800 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
|
H A D | X86ISelLowering.cpp | 1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 11 // selection DAG. 73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1, 77 SelectionDAG &DAG, SDLoc dl, 84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 89 return DAG.getUNDEF(ResultVT); 101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT, 105 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal); 106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 112 /// Generate a DAG t 76 ExtractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl, unsigned vectorWidth) argument 118 Extract128BitVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl) argument 126 Extract256BitVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl) argument 132 InsertSubVector(SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl, unsigned vectorWidth) argument 162 Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl) argument 169 Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl) argument 180 Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, unsigned NumElems, SelectionDAG &DAG, SDLoc dl) argument 187 Concat256BitVectors(SDValue V1, SDValue V2, EVT VT, unsigned NumElems, SelectionDAG &DAG, SDLoc dl) argument 2036 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 2144 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl) argument 2187 LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo *MFI, unsigned i) const argument 2228 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 2515 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument 2534 EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall, bool Is64Bit, int FPDiff, SDLoc dl) const argument 2550 EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT, unsigned SlotSize, int FPDiff, SDLoc dl) argument 2570 SelectionDAG &DAG = CLI.DAG; local 3389 getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, SDValue V1, SelectionDAG &DAG) argument 3400 getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, SDValue V1, unsigned TargetMask, SelectionDAG &DAG) argument 3414 getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) argument 3427 getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG) argument 3539 TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) argument 4022 Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) argument 4756 CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) argument 4891 getZeroVector(EVT VT, const X86Subtarget *Subtarget, SelectionDAG &DAG, SDLoc dl) argument 4938 getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG, SDLoc dl) argument 4972 getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1, SDValue V2) argument 4983 getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, SDValue V2) argument 4995 getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, SDValue V2) argument 5010 PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) argument 5028 getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) argument 5054 PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) argument 5096 getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, bool IsZero, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument 5194 getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, unsigned Depth) argument 5260 getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems, bool ZerosFromLeft, SelectionDAG &DAG, unsigned PreferredNum = -1U) argument 5314 isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, bool &isLeft, SDValue &ShVal, unsigned &ShAmt) argument 5349 isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, bool &isLeft, SDValue &ShVal, unsigned &ShAmt) argument 5384 isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, bool &isLeft, SDValue &ShVal, unsigned &ShAmt) argument 5400 LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget* Subtarget, const TargetLowering &TLI) argument 5448 LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget* Subtarget, const TargetLowering &TLI) argument 5479 LowerBuildVectorv4x32(SDValue Op, unsigned NumElems, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget *Subtarget, const TargetLowering &TLI) argument 5553 getVShift(bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits, SelectionDAG &DAG, const TargetLowering &TLI, SDLoc dl) argument 5567 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) argument 5649 EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, SDLoc &DL, SelectionDAG &DAG, bool isAfterLegalize) argument 5749 LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget, SelectionDAG &DAG) argument 5919 buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) argument 6085 isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode, SelectionDAG &DAG, unsigned BaseIdx, unsigned LastIdx, SDValue &V0, SDValue &V1) argument 6193 ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1, SDLoc DL, SelectionDAG &DAG, unsigned X86Opcode, bool Mode, bool isUndefLO, bool isUndefHI) argument 6233 matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG, const X86Subtarget *Subtarget) argument 6352 PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) argument 6848 LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) argument 6872 LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) argument 6934 getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SelectionDAG &DAG) argument 6957 lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument 6989 lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument 7029 lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument [all...] |
/external/llvm/lib/Transforms/Vectorize/ |
H A D | BBVectorize.cpp | 315 DenseMap<ValuePair, size_t> &DAG, 326 DenseMap<ValuePair, size_t> &DAG, ValuePair J); 1584 DenseMap<ValuePair, size_t> &DAG, ValuePair J) { 1585 // Each of these pairs is viewed as the root node of a DAG. The DAG 1587 // the pairs that compose the DAG and the maximum depth of the DAG. 1604 DenseMap<ValuePair, size_t>::iterator C = DAG.find(*k); 1605 if (C == DAG.end()) { 1616 // Record the current pair as part of the DAG 1577 buildInitialDAGFor( DenseMap<Value *, std::vector<Value *> > &CandidatePairs, DenseSet<ValuePair> &CandidatePairsSet, std::vector<Value *> &PairableInsts, DenseMap<ValuePair, std::vector<ValuePair> > &ConnectedPairs, DenseSet<ValuePair> &PairableInstUsers, DenseMap<Value *, Value *> &ChosenPairs, DenseMap<ValuePair, size_t> &DAG, ValuePair J) argument 1625 pruneDAGFor( DenseMap<Value *, std::vector<Value *> > &CandidatePairs, std::vector<Value *> &PairableInsts, DenseMap<ValuePair, std::vector<ValuePair> > &ConnectedPairs, DenseSet<ValuePair> &PairableInstUsers, DenseMap<ValuePair, std::vector<ValuePair> > &PairableInstUserMap, DenseSet<VPPair> &PairableInstUserPairSet, DenseMap<Value *, Value *> &ChosenPairs, DenseMap<ValuePair, size_t> &DAG, DenseSet<ValuePair> &PrunedDAG, ValuePair J, bool UseCycleCheck) argument 1843 DenseMap<ValuePair, size_t> DAG; local [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===// 562 SelectionDAG &DAG) const { 569 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), 576 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), 583 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), 590 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), 597 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), 602 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 625 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL, argument 631 Value = DAG 650 convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL, CCValAssign &VA, SDValue Value) argument 667 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 805 SelectionDAG &DAG = CLI.DAG; local 1114 adjustZeroCmp(SelectionDAG &DAG, Comparison &C) argument 1134 adjustSubwordCmp(SelectionDAG &DAG, Comparison &C) argument 1295 adjustForSubtraction(SelectionDAG &DAG, Comparison &C) argument 1360 adjustICmpTruncate(SelectionDAG &DAG, Comparison &C) argument 1491 adjustForTestUnderMask(SelectionDAG &DAG, Comparison &C) argument 1573 getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1, ISD::CondCode Cond) argument 1615 emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) argument 1631 lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL, unsigned Extend, SDValue Op0, SDValue Op1, SDValue &Hi, SDValue &Lo) argument 1647 lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT, unsigned Extend, unsigned Opcode, SDValue Op0, SDValue Op1, SDValue &Even, SDValue &Odd) argument 1662 emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue, unsigned CCValid, unsigned CCMask) argument 1724 getAbsolute(SelectionDAG &DAG, SDLoc DL, SDValue Op, bool IsNegative) argument 2212 lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG, unsigned Opcode) const argument 2533 SelectionDAG &DAG = DCI.DAG; local [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===// 570 const SelectionDAG &DAG, unsigned Depth) const { 576 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1); 577 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1); 849 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64 878 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC. 939 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 978 SDLoc dl, SelectionDAG &DAG) { 982 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS); 1016 return DAG 568 computeKnownBitsForTargetNode( const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument 977 emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG) argument 1020 getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) argument 1084 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) argument 1196 LowerF128Call(SDValue Op, SelectionDAG &DAG, RTLIB::Libcall Call) const argument 1206 LowerXOR(SDValue Op, SelectionDAG &DAG) argument 1265 LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) argument 1301 LowerXALUO(SDValue Op, SelectionDAG &DAG) argument 1331 LowerPREFETCH(SDValue Op, SelectionDAG &DAG) argument 1385 LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) argument 1434 LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) argument 1644 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1838 saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL, SDValue &Chain) const argument 1913 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn, SDValue ThisVal) const argument 2066 addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo *MFI, int ClobberedFI) const argument 2113 SelectionDAG &DAG = CLI.DAG; local 4081 WidenVector(SDValue V64Reg, SelectionDAG &DAG) argument 4101 NarrowVector(SDValue V128Reg, SelectionDAG &DAG) argument 4512 tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) argument 4543 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl) argument 4644 GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask, SelectionDAG &DAG) argument 5026 tryLowerToSLI(SDNode *N, SelectionDAG &DAG) argument 5190 NormalizeBuildVector(SDValue Op, SelectionDAG &DAG) argument 5826 EmitVectorComparison(SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, SDLoc dl, SelectionDAG &DAG) argument 6325 performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) argument 6353 performXorCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument 6362 performMulCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument 6420 performIntToFpCombine(SDNode *N, SelectionDAG &DAG) argument 6479 SelectionDAG &DAG = DCI.DAG; local 6520 SelectionDAG &DAG = DCI.DAG; local 6586 performBitcastCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 6652 performConcatVectorsCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 6701 tryCombineFixedPointConvert(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 6761 tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) argument 6895 performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) argument 6944 performAddSubLongCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 6993 tryCombineLongOpWithDup(unsigned IID, SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 7022 tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) argument 7082 tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) argument 7098 SelectionDAG &DAG = DCI.DAG; local 7134 performExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 7237 replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) argument 7292 performSTORECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument 7452 performNEONPostLDSTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 7583 performBRCONDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 7641 performVSelectCombine(SDNode *N, SelectionDAG &DAG) argument 7670 performSelectCombine(SDNode *N, SelectionDAG &DAG) argument 7706 SelectionDAG &DAG = DCI.DAG; local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 11 // selection DAG. 450 // In another words, find a way when "copysign" appears in DAG with vector 1138 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 1155 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. 1253 SDLoc dl, SelectionDAG &DAG, 1259 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1260 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1281 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1286 SDValue Hi = DAG 1250 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn, SDValue ThisVal) const argument 1336 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument 1349 PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVectorImpl<SDValue> &MemOpChains, ISD::ArgFlagsTy Flags) const argument 1381 SelectionDAG &DAG = CLI.DAG; local 2046 LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, SDLoc DL, SelectionDAG &DAG) argument 2267 LowerConstantPool(SDValue Op, SelectionDAG &DAG) argument 2360 LowerToTLSExecModels(GlobalAddressSDNode *GA, SelectionDAG &DAG, TLSModel::Model model) const argument 2563 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const argument 2613 LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 2645 LowerPREFETCH(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 2672 LowerVASTART(SDValue Op, SelectionDAG &DAG) argument 2687 GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, SDLoc dl) const argument 2777 StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, SDLoc dl, SDValue &Chain, const Value *OrigArg, unsigned InRegsParamRecordIdx, unsigned OffsetFromOrigArg, unsigned ArgOffset, unsigned ArgSize, bool ForceMutable, unsigned ByValStoreOffset, unsigned TotalArgRegsSaveSize) const argument 2883 VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc dl, SDValue &Chain, unsigned ArgOffset, unsigned TotalArgRegsSaveSize, bool ForceMutable) const argument 2905 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 3140 getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const argument 3199 getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl) const argument 3231 getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const argument 3530 bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) argument 3543 expandf64Toi32(SDValue Op, SelectionDAG &DAG, SDValue &RetVal1, SDValue &RetVal2) argument 3708 LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) argument 3727 LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) argument 3748 LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) argument 3781 LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) argument 3945 ExpandBITCAST(SDNode *N, SelectionDAG &DAG) argument 3991 getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) argument 4088 LowerCTTZ(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 4113 getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) argument 4135 lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) argument 4170 lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) argument 4193 LowerCTPOP(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 4208 LowerShift(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 4243 Expand64BitShift(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 4281 LowerVSETCC(SDValue Op, SelectionDAG &DAG) argument 4415 isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, EVT &VT, bool is128Bits, NEONModImmType type) argument 4550 LowerConstantFP(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) const argument 4878 IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST, SDLoc dl) argument 4897 LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) const argument 5297 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl) argument 5373 LowerVECTOR_SHUFFLEv8i8(SDValue Op, ArrayRef<int> ShuffleMask, SelectionDAG &DAG) argument 5394 LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op, SelectionDAG &DAG) argument 5411 LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) argument 5560 LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) argument 5569 LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) argument 5585 LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) argument 5608 isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, bool isSigned) argument 5661 isSignExtended(SDNode *N, SelectionDAG &DAG) argument 5671 isZeroExtended(SDNode *N, SelectionDAG &DAG) argument 5699 AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode) argument 5721 SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) argument 5746 SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) argument 5784 isAddSubSExt(SDNode *N, SelectionDAG &DAG) argument 5795 isAddSubZExt(SDNode *N, SelectionDAG &DAG) argument 5806 LowerMUL(SDValue Op, SelectionDAG &DAG) argument 5882 LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) argument 5911 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) argument 5947 LowerSDIV(SDValue Op, SelectionDAG &DAG) argument 5982 LowerUDIV(SDValue Op, SelectionDAG &DAG) argument 6056 LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) argument 6141 LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) argument 6151 ReplaceREADCYCLECOUNTER(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 7576 isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG) argument 7651 SelectionDAG &DAG = DCI.DAG; local 7753 SelectionDAG &DAG = DCI.DAG; local 8035 SelectionDAG &DAG = DCI.DAG; local 8124 SelectionDAG &DAG = DCI.DAG; local 8167 SelectionDAG &DAG = DCI.DAG; local 8361 SelectionDAG &DAG = DCI.DAG; local 8416 SelectionDAG &DAG = DCI.DAG; local 8445 PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) argument 8475 SelectionDAG &DAG = DCI.DAG; local 8558 SelectionDAG &DAG = DCI.DAG; local 8624 SelectionDAG &DAG = DCI.DAG; local 8770 PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) argument 8957 SelectionDAG &DAG = DCI.DAG; local 9103 SelectionDAG &DAG = DCI.DAG; local 9154 SelectionDAG &DAG = DCI.DAG; local 9243 PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) argument 9388 PerformShiftCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 9435 PerformExtendCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 9475 PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) argument 10019 getARMIndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) argument 10078 getT2IndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) argument 10193 computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 857 SelectionDAG &DAG) { 858 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1; 875 SelectionDAG &DAG) { 877 if (DAG.getTarget().getDataLayout()->isLittleEndian()) { 923 bool isUnary, SelectionDAG &DAG) { 924 if (DAG.getTarget().getDataLayout()->isLittleEndian()) { 938 bool isUnary, SelectionDAG &DAG) { 939 if (DAG.getTarget().getDataLayout()->isLittleEndian()) { 953 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) { argument 856 isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary, SelectionDAG &DAG) argument 874 isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary, SelectionDAG &DAG) argument 922 isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, bool isUnary, SelectionDAG &DAG) argument 937 isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, bool isUnary, SelectionDAG &DAG) argument 1054 getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG) argument 1068 get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) argument 1251 fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) argument 1287 SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, bool Aligned) const argument 1518 LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG) argument 1782 LowerVAARG(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const argument 1890 LowerVACOPY(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const argument 1946 LowerVASTART(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const argument 2173 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 2194 LowerFormalArguments_32SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 2417 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, SDValue ArgVal, SDLoc dl) const argument 2431 LowerFormalArguments_64SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 2706 LowerFormalArguments_Darwin( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 3073 CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, unsigned ParamSize) argument 3129 isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) argument 3156 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, SDValue Chain, const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs, SmallVectorImpl<SDValue> &MemOpChains, SDLoc dl) argument 3174 EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, bool isPPC64, bool isDarwinABI, SDLoc dl) argument 3215 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) argument 3233 EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, int SPDiff, SDValue Chain, SDValue &LROpOut, SDValue &FPOpOut, bool isDarwinABI, SDLoc dl) const argument 3267 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl) argument 3279 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, SDLoc dl) argument 3304 PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, bool isDarwinABI, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) argument 3331 PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall, SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass, SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys, const PPCSubtarget &Subtarget) argument 3518 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 3564 FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall, bool isVarArg, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue InFlag, SDValue Chain, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<SDValue> &InVals) const argument 3669 SelectionDAG &DAG = CLI.DAG; local 3705 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 3924 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl) const argument 3942 LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 4357 LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 4809 LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const argument 4891 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const argument 5077 LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const argument 5430 BuildSplatI(int Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, SDLoc dl) argument 5456 BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG, SDLoc dl, EVT DestVT = MVT::Other) argument 5466 BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl, EVT DestVT = MVT::Other) argument 5476 BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, SDLoc dl, EVT DestVT = MVT::Other) argument 5487 BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, SDLoc dl) argument 5681 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl) argument 7161 SelectionDAG &DAG = DCI.DAG; local 7224 SelectionDAG &DAG = DCI.DAG; local 7271 isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG) argument 7314 findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) argument 7379 SelectionDAG &DAG = DCI.DAG; local 7658 SelectionDAG &DAG = DCI.DAG; local 7908 SelectionDAG &DAG = DCI.DAG; local 8493 computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument [all...] |