/external/llvm/lib/Target/PowerPC/ |
H A D | PPCJITInfo.cpp | 28 PPCJITInfo::PPCJITInfo(PPCSubtarget &STI) argument 29 : Subtarget(STI), is64Bit(STI.isPPC64()) {
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | AMDGPUMCTargetDesc.cpp | 70 const MCSubtargetInfo &STI) { 76 const MCSubtargetInfo &STI, 78 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { 79 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx); 81 return createR600MCCodeEmitter(MCII, MRI, STI); 89 const MCSubtargetInfo &STI, 65 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument 74 createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument 85 createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) argument
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H A D | R600MCCodeEmitter.cpp | 46 const MCSubtargetInfo &STI) const override; 51 const MCSubtargetInfo &STI) const override; 85 const MCSubtargetInfo &STI) { 91 const MCSubtargetInfo &STI) const { 100 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI); 102 if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) { 124 uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI); 134 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI); 135 if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) && 173 const MCSubtargetInfo &STI) cons 83 createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument [all...] |
H A D | SIMCCodeEmitter.cpp | 59 const MCSubtargetInfo &STI) const override; 64 const MCSubtargetInfo &STI) const override; 71 const MCSubtargetInfo &STI, 131 const MCSubtargetInfo &STI) const { 133 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI); 175 const MCSubtargetInfo &STI) const { 69 createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 37 MCSubtargetInfo &STI; member in class:__anon26131::SparcAsmParser 79 bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); } 84 : MCTargetAsmParser(), STI(sti), Parser(parser) { 86 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 401 Out.EmitInstruction(Inst, STI);
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/external/llvm/lib/Target/Sparc/Disassembler/ |
H A D | SparcDisassembler.cpp | 35 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : argument 36 MCDisassembler(STI, Ctx) 57 const MCSubtargetInfo &STI, 59 return new SparcDisassembler(STI, Ctx); 256 this, STI); 55 createSparcDisassembler( const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/Sparc/InstPrinter/ |
H A D | SparcInstPrinter.h | 25 const MCSubtargetInfo &STI; member in class:llvm::SparcInstPrinter 31 : MCInstPrinter(MAI, MII, MRI), STI(sti) {}
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCCodeEmitter.cpp | 45 const MCSubtargetInfo &STI) const override; 51 const MCSubtargetInfo &STI) const; 57 const MCSubtargetInfo &STI) const; 61 const MCSubtargetInfo &STI) const; 64 const MCSubtargetInfo &STI) const; 67 const MCSubtargetInfo &STI) const; 70 const MCSubtargetInfo &STI) const; 77 const MCSubtargetInfo &STI, 85 const MCSubtargetInfo &STI) const { 86 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI); 75 createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument [all...] |
H A D | SparcMCTargetDesc.cpp | 128 const MCSubtargetInfo &STI, bool RelaxAll, 153 const MCSubtargetInfo &STI) { 154 return new SparcInstPrinter(MAI, MII, MRI, STI); 125 createMCStreamer(const Target &T, StringRef TT, MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) argument 148 createSparcMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcAsmPrinter.cpp | 74 const MCSubtargetInfo &STI); 112 const MCSubtargetInfo &STI) 117 OutStreamer.EmitInstruction(CallInst, STI); 122 const MCSubtargetInfo &STI) 128 OutStreamer.EmitInstruction(SETHIInst, STI); 133 const MCSubtargetInfo &STI) 140 OutStreamer.EmitInstruction(Inst, STI); 145 const MCSubtargetInfo &STI) { 146 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI); 151 const MCSubtargetInfo &STI) { 110 EmitCall(MCStreamer &OutStreamer, MCOperand &Callee, const MCSubtargetInfo &STI) argument 120 EmitSETHI(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument 131 EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI) argument 143 EmitOR(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument 149 EmitADD(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &RS2, MCOperand &RD, const MCSubtargetInfo &STI) argument 155 EmitSHL(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument 162 EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym, SparcMCExpr::VariantKind HiKind, SparcMCExpr::VariantKind LoKind, MCOperand &RD, MCContext &OutContext, const MCSubtargetInfo &STI) argument 175 LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, const MCSubtargetInfo &STI) argument [all...] |
/external/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 298 MCSubtargetInfo &STI; member in class:__anon26144::SystemZAsmParser 334 : MCTargetAsmParser(), STI(sti), Parser(parser) { 338 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 691 Out.EmitInstruction(Inst, STI);
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/external/llvm/lib/Target/SystemZ/Disassembler/ |
H A D | SystemZDisassembler.cpp | 27 SystemZDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) argument 28 : MCDisassembler(STI, Ctx) {} 40 const MCSubtargetInfo &STI, 42 return new SystemZDisassembler(STI, Ctx); 323 return decodeInstruction(Table, MI, Inst, Address, this, STI); 39 createSystemZDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCTargetDesc.cpp | 180 const MCSubtargetInfo &STI) { 189 const MCSubtargetInfo &STI, 175 createSystemZMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument 184 createSystemZMCObjectStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) argument
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.h | 116 SystemZSubtarget &STI; member in class:llvm::SystemZInstrInfo 134 explicit SystemZInstrInfo(SystemZSubtarget &STI);
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/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmInstrumentation.cpp | 46 X86AddressSanitizer(const MCSubtargetInfo &STI) : STI(STI) {} argument 69 Out.EmitInstruction(Inst, STI); 75 const MCSubtargetInfo &STI; member in class:llvm::__anon26164::X86AddressSanitizer 147 X86AddressSanitizer32(const MCSubtargetInfo &STI) argument 148 : X86AddressSanitizer(STI) {} 313 X86AddressSanitizer64(const MCSubtargetInfo &STI) argument 314 : X86AddressSanitizer(STI) {} 494 const MCContext &Ctx, const MCSubtargetInfo &STI) { 493 CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions, const MCContext &Ctx, const MCSubtargetInfo &STI) argument [all...] |
H A D | X86AsmParser.cpp | 57 MCSubtargetInfo &STI; member in class:__anon26165::X86AsmParser 712 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; 716 return (STI.getFeatureBits() & X86::Mode32Bit) != 0; 720 return (STI.getFeatureBits() & X86::Mode16Bit) != 0; 723 uint64_t oldMode = STI.getFeatureBits() & 725 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(oldMode | mode)); 727 assert(mode == (STI.getFeatureBits() & 747 : MCTargetAsmParser(), STI(sti), Parser(parser), MII(mii), 751 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 753 CreateX86AsmInstrumentation(Options, Parser.getContext(), STI)); [all...] |
/external/llvm/lib/Target/X86/Disassembler/ |
H A D | X86Disassembler.cpp | 80 const MCSubtargetInfo &STI, 83 : MCDisassembler(STI, Ctx), MII(std::move(MII)) { 84 switch (STI.getFeatureBits() & 804 const MCSubtargetInfo &STI, 807 return new X86Disassembler::X86GenericDisassembler(STI, Ctx, std::move(MII)); 79 X86GenericDisassembler( const MCSubtargetInfo &STI, MCContext &Ctx, std::unique_ptr<const MCInstrInfo> MII) argument 803 createX86Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 44 bool is64BitMode(const MCSubtargetInfo &STI) const { 45 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; 48 bool is32BitMode(const MCSubtargetInfo &STI) const { 49 return (STI.getFeatureBits() & X86::Mode32Bit) != 0; 52 bool is16BitMode(const MCSubtargetInfo &STI) const { 53 return (STI.getFeatureBits() & X86::Mode16Bit) != 0; 59 const MCSubtargetInfo &STI) const { 64 if (is16BitMode(STI) && BaseReg.getReg() == 0 && 150 const MCSubtargetInfo &STI) const; 154 const MCSubtargetInfo &STI) cons 1125 EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, const MCInst &MI, const MCInstrDesc &Desc, const MCSubtargetInfo &STI, raw_ostream &OS) const argument [all...] |
H A D | X86MCTargetDesc.cpp | 355 const MCSubtargetInfo &STI, 377 const MCSubtargetInfo &STI) { 351 createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) argument 372 createX86MCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 101 X86InstrInfo::X86InstrInfo(X86Subtarget &STI) argument 103 (STI.is64Bit() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32), 104 (STI.is64Bit() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)), 105 Subtarget(STI), RI(STI) { 3182 const X86Subtarget &STI, 3184 if (STI.hasAVX512()) { 3196 bool HasAVX = STI.hasAVX(); 3202 if (STI.is64Bit()) 3269 const X86Subtarget &STI) { 3179 getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI, bool load) argument 3266 getStoreRegOpcode(unsigned SrcReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI) argument 3274 getLoadRegOpcode(unsigned DestReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI) argument [all...] |
H A D | X86MCInstLower.cpp | 608 const MCSubtargetInfo& STI) { 618 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); local 665 OutStreamer.EmitInstruction(LEA, STI); 668 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); local 669 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); local 670 OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX), STI); local 682 .addExpr(tlsRef), STI); local 686 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) { argument 721 OS.EmitInstruction(MCInstBuilder(Opc), STI); local 724 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI); local 605 LowerTlsAddr(MCStreamer &OutStreamer, X86MCInstLower &MCInstLowering, const MachineInstr &MI, const MCSubtargetInfo& STI) argument 731 .addReg(SegmentReg), STI); local 739 LowerSTACKMAP(MCStreamer &OS, StackMaps &SM, const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) argument 752 LowerPATCHPOINT(MCStreamer &OS, StackMaps &SM, const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) argument 770 .addImm(CallTarget), STI); local 771 OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg), STI); local [all...] |
H A D | X86RegisterInfo.cpp | 56 X86RegisterInfo::X86RegisterInfo(const X86Subtarget &STI) argument 58 (STI.is64Bit() ? X86::RIP : X86::EIP), 59 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), false), 60 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), true), 61 (STI.is64Bit() ? X86::RIP : X86::EIP)), 62 Subtarget(STI) {
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/external/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 36 XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : argument 37 MCDisassembler(STI, Ctx) {} 766 Address, this, STI); 779 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI); 793 const MCSubtargetInfo &STI, 795 return new XCoreDisassembler(STI, Ctx); 792 createXCoreDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/XCore/MCTargetDesc/ |
H A D | XCoreMCTargetDesc.cpp | 89 const MCSubtargetInfo &STI) { 84 createXCoreMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/chromium_org/third_party/mesa/src/src/mesa/x86/ |
H A D | assyntax.h | 663 #define STI CHOICE(sti, sti, sti) macro 1384 #define STI sti macro
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