Searched refs:TII (Results 76 - 100 of 224) sorted by relevance

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/external/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp93 const X86InstrInfo *TII; // Machine instruction info. member in class:__anon26188::FixupLEAPass
109 TII->get(MI->getOpcode() == X86::MOV32rr ? X86::LEA32r
147 return TII->convertToThreeAddress(MFI, MBBI, nullptr);
159 TII = static_cast<const X86InstrInfo *>(TM->getInstrInfo());
221 InstrDistance += TII->getInstrLatency(TM->getInstrItineraryData(), CurInst);
274 !TII->isSafeToClobberEFLAGS(*MFI, I))
309 NewMI = BuildMI(*MF, MI->getDebugLoc(), TII->get(addrr_opcode))
319 NewMI = BuildMI(*MF, MI->getDebugLoc(), TII->get(addri_opcode))
H A DX86FastISel.cpp414 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
437 TII.get(X86::AND8ri), AndResult)
478 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
512 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
616 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), LoadReg);
1057 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
1074 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
1081 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Subtarget->is64Bit() ? X86::RETQ : X86::RETL));
1165 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CompareImmOpc))
1177 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII
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/external/llvm/lib/Target/R600/
H A DSIFixSGPRCopies.cpp200 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( local
212 TII->moveToVALU(MI);
243 TII->moveToVALU(MI);
251 if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) ||
258 TII->moveToVALU(MI);
270 TII->moveToVALU(MI);
H A DR600ISelLowering.cpp191 const R600InstrInfo *TII = local
198 if (TII->isLDSRetInstr(MI->getOpcode())) {
199 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
206 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode())));
215 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
219 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
224 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
228 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
233 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
237 TII
645 const R600InstrInfo *TII = local
2055 const R600InstrInfo *TII = local
2180 const R600InstrInfo *TII = local
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H A DR600ControlFlowFinalizer.cpp219 const R600InstrInfo *TII; member in class:__anon26114::R600ControlFlowFinalizer
277 return TII->get(Opcode);
320 bool IsTex = TII->usesTextureCache(ClauseHead);
327 if ((IsTex && !TII->usesTextureCache(I)) ||
328 (!IsTex && !TII->usesVertexCache(I)))
350 TII->getSrcs(MI);
376 TII->get(AMDGPU::LITERALS))
394 if (!I->isBundle() && !TII->isALUInstr(I->getOpcode()))
421 TII->get(AMDGPU::LITERALS))
437 BuildMI(BB, InsertPos->getDebugLoc(), TII
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H A DSIInsertWaits.cpp49 const SIInstrInfo *TII; member in class:__anon26125::SIInsertWaits
100 TII(nullptr),
125 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags;
137 if (TII->isSMRD(MI.getOpcode())) {
298 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
349 TII = static_cast<const SIInstrInfo*>(MF.getTarget().getInstrInfo());
/external/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp142 const TargetInstrInfo *TII; member in class:__anon25935::SSACCmpConv
194 TII = MF.getTarget().getInstrInfo();
419 if (!I.isSafeToMove(TII, nullptr, DontMoveAcrossStore)) {
499 if (TII->AnalyzeBranch(*Head, TBB, FBB, HeadCond)) {
527 if (TII->AnalyzeBranch(*CmpBB, TBB, FBB, CmpBBCond)) {
574 TII->RemoveBranch(*Head);
593 const MCInstrDesc &MCID = TII->get(Opc);
596 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
605 TII->getRegClass(MCID, 1, TRI, *MF));
650 const MCInstrDesc &MCID = TII
724 const TargetInstrInfo *TII; member in class:__anon25936::AArch64ConditionalCompares
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H A DAArch64FrameLowering.cpp111 const AArch64InstrInfo *TII = local
115 bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode();
142 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, Amount, TII);
149 TII);
161 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
197 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
209 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); local
229 emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -NumBytes, TII,
235 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
276 emitFrameOffset(MBB, MBBI, DL, AArch64::FP, AArch64::SP, FPOffset, TII,
437 const AArch64InstrInfo *TII = local
620 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
696 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
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H A DAArch64FastISel.cpp187 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
218 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
231 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
263 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
268 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
275 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
279 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
471 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
580 TII
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H A DAArch64RegisterInfo.cpp38 : AArch64GenRegisterInfo(AArch64::LR), TII(tii), STI(sti) {}
294 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
297 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
315 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
348 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
359 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp84 const TargetInstrInfo &TII; member in class:__anon25970::final
98 TII(*TM.getInstrInfo()),
290 const MCInstrDesc &II = TII.get(MachineInstOpcode);
302 TII.get(TargetOpcode::COPY), ResultReg)
313 const MCInstrDesc &II = TII.get(MachineInstOpcode);
330 TII.get(TargetOpcode::COPY), ResultReg)
342 const MCInstrDesc &II = TII.get(MachineInstOpcode);
362 TII.get(TargetOpcode::COPY), ResultReg)
373 const MCInstrDesc &II = TII.get(MachineInstOpcode);
388 TII
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H A DARMBaseRegisterInfo.cpp405 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
411 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
594 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
595 const MCInstrDesc &MCID = TII.get(ADDriOpc);
596 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
609 const ARMBaseInstrInfo &TII = local
624 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
627 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
708 const ARMBaseInstrInfo &TII = local
740 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
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H A DARMInstrInfo.cpp127 const TargetInstrInfo &TII = *TM->getInstrInfo(); variable
129 TII.get(Opc), TempReg)
139 MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
/external/llvm/lib/Target/Mips/
H A DMips16ISelLowering.cpp520 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
552 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
569 TII->get(Mips::PHI), MI->getOperand(0).getReg())
582 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
614 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
616 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
632 TII->get(Mips::PHI), MI->getOperand(0).getReg())
646 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
678 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
680 BuildMI(BB, DL, TII
711 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
727 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
761 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
778 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local
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H A DMips16ISelDAGToDAG.cpp74 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
84 BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0).
89 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
90 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
105 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
109 BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
H A DMipsConstantIslandPass.cpp348 const Mips16InstrInfo *TII; member in class:__anon26048::MipsConstantIslands
458 TII = (const Mips16InstrInfo*)MF->getTarget().getInstrInfo();
580 BuildMI(*BB, InsAt, DebugLoc(), TII->get(Mips::CONSTPOOL_ENTRY))
822 BBI.Size += TII->GetInstSizeInBytes(I);
840 Offset += TII->GetInstSizeInBytes(I);
896 BuildMI(OrigBB, DebugLoc(), TII->get(Mips::Bimm16)).addMBB(NewBB);
1144 UserMI->setDesc(TII->get(U.getLongFormOpcode()));
1275 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1319 for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI);
1321 Offset += TII
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/external/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp67 : MachineFunctionPass(ID), TII(nullptr), TRI(nullptr) {}
88 const SystemZInstrInfo *TII; member in class:__anon26150::SystemZElimCompare
202 Branch->setDesc(TII->get(BRCT));
215 unsigned Opcode = TII->getLoadAndTest(MI->getOpcode());
219 MI->setDesc(TII->get(Opcode));
234 const MCInstrDesc &Desc = TII->get(Opcode);
368 unsigned FusedOpcode = TII->getCompareAndBranch(Compare->getOpcode(),
405 Branch->setDesc(TII->get(FusedOpcode));
461 TII = static_cast<const SystemZInstrInfo *>(F.getTarget().getInstrInfo());
462 TRI = &TII
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/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp87 const TargetInstrInfo &TII; member in class:__anon26084::final
97 TII(*TM.getInstrInfo()),
408 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
500 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
506 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
530 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
616 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
624 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
644 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
708 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII
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/external/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp68 const HexagonInstrInfo *TII; member in struct:__anon26012::HexagonHardwareLoops
305 TII = static_cast<const HexagonInstrInfo*>(TM->getInstrInfo());
374 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
388 bool CmpAnalyzed = TII->analyzeCompare(PredI, CmpReg1, CmpReg2,
482 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
506 bool AnalyzedCmp = TII->analyzeCompare(CondI, CmpReg1, CmpReg2,
781 const MCInstrDesc &SubD = RegToReg ? TII->get(Hexagon::SUB_rr) :
782 (RegToImm ? TII->get(Hexagon::SUB_ri) :
783 TII->get(Hexagon::ADD_ri));
811 const MCInstrDesc &AddD = TII
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/external/llvm/lib/CodeGen/
H A DMachineSSAUpdater.cpp42 TII = MF.getTarget().getInstrInfo();
118 const TargetInstrInfo *TII) {
120 return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR);
153 VRC, MRI, TII);
189 Loc, VRC, MRI, TII);
291 Updater->TII);
302 Updater->TII);
114 InsertNewDef(unsigned Opcode, MachineBasicBlock *BB, MachineBasicBlock::iterator I, const TargetRegisterClass *RC, MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument
H A DDeadMachineInstructionElim.cpp35 const TargetInstrInfo *TII; member in class:__anon25737::DeadMachineInstructionElim
63 if (!MI->isSafeToMove(TII, nullptr, SawStore) && !MI->isPHI())
94 TII = MF.getTarget().getInstrInfo();
H A DProcessImplicitDefs.cpp28 const TargetInstrInfo *TII; member in class:__anon25785::ProcessImplicitDefs
89 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
141 TII = MF.getTarget().getInstrInfo();
H A DMachineBasicBlock.cpp362 const TargetInstrInfo &TII = *getParent()->getTarget().getInstrInfo(); local
376 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
393 const TargetInstrInfo *TII = getParent()->getTarget().getInstrInfo(); local
400 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
408 TII->RemoveBranch(*this);
428 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
436 if (TII->ReverseBranchCondition(Cond))
438 TII->RemoveBranch(*this);
439 TII->InsertBranch(*this, FBB, nullptr, Cond, dl);
441 TII
648 const TargetInstrInfo *TII = getParent()->getTarget().getInstrInfo(); local
693 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); local
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp237 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
644 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
645 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
650 TII.get(TargetOpcode::STACKMAP));
655 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
656 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
681 TII.get(TargetOpcode::INLINEASM))
752 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0,
756 TII.get(TargetOpcode::DBG_VALUE))
770 const MCInstrDesc &II = TII
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H A DScheduleDAGSDNodes.cpp113 const TargetInstrInfo *TII,
124 const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
232 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
263 if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
305 const MCInstrDesc &MCID = TII->get(Opc);
364 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
382 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
440 const MCInstrDesc &MCID = TII->get(Opc);
454 TII->get(N->getMachineOpcode()).getImplicitDefs()) {
459 if (NumUsed > TII
111 CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) argument
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