Searched refs:BaseOffs (Results 1 - 14 of 14) sorted by relevance
/external/llvm/lib/CodeGen/ |
H A D | CodeGenPrepare.cpp | 1048 (BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) && 1070 if (BaseOffs) { 1072 << BaseOffs; 1613 TestAddrMode.BaseOffs += CI->getSExtValue()*TestAddrMode.Scale; 2080 AddrMode.BaseOffs += ConstantOffset; 2086 AddrMode.BaseOffs -= ConstantOffset; 2095 AddrMode.BaseOffs += ConstantOffset; 2120 AddrMode.BaseOffs += ConstantOffset; 2192 AddrMode.BaseOffs [all...] |
H A D | BasicTargetTransformInfo.cpp | 153 AM.BaseOffs = BaseOffset; 164 AM.BaseOffs = BaseOffset;
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H A D | TargetLoweringBase.cpp | 1434 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1446 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1451 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
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/external/llvm/lib/Analysis/ |
H A D | BasicAliasAnalysis.cpp | 290 DecomposeGEPExpression(const Value *V, int64_t &BaseOffs, argument 297 BaseOffs = 0; 358 BaseOffs += DL->getStructLayout(STy)->getElementOffset(FieldNo); 365 BaseOffs += DL->getTypeAllocSize(*GTI)*CIdx->getSExtValue(); 385 BaseOffs += IndexOffset.getSExtValue()*Scale;
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1913 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); 1919 AM.BaseOffs%4 == 0; 1926 return isImmUs(AM.BaseOffs); 1929 return AM.Scale == 1 && AM.BaseOffs == 0; 1934 return isImmUs2(AM.BaseOffs); 1937 return AM.Scale == 2 && AM.BaseOffs == 0; 1941 return isImmUs4(AM.BaseOffs); 1944 return AM.Scale == 4 && AM.BaseOffs == 0;
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/external/llvm/include/llvm/Target/ |
H A D | TargetLowering.h | 1243 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1245 /// If BaseOffs is zero, there is no base offset. 1251 int64_t BaseOffs; 1254 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1634 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) {
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 2561 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 2570 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 8749 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 8761 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 8766 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 6204 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) 6218 int64_t Offset = AM.BaseOffs;
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 361 if (!isInt<20>(AM.BaseOffs))
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 7561 AM.BaseOffs = Offset->getSExtValue(); 7569 AM.BaseOffs = -Offset->getSExtValue();
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 9934 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) 9950 if (AM.BaseOffs)
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 16653 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr)) 16671 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
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