Searched refs:BaseOffs (Results 1 - 14 of 14) sorted by relevance

/external/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp1048 (BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) &&
1070 if (BaseOffs) {
1072 << BaseOffs;
1613 TestAddrMode.BaseOffs += CI->getSExtValue()*TestAddrMode.Scale;
2080 AddrMode.BaseOffs += ConstantOffset;
2086 AddrMode.BaseOffs -= ConstantOffset;
2095 AddrMode.BaseOffs += ConstantOffset;
2120 AddrMode.BaseOffs += ConstantOffset;
2192 AddrMode.BaseOffs
[all...]
H A DBasicTargetTransformInfo.cpp153 AM.BaseOffs = BaseOffset;
164 AM.BaseOffs = BaseOffset;
H A DTargetLoweringBase.cpp1434 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1446 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1451 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
/external/llvm/lib/Analysis/
H A DBasicAliasAnalysis.cpp290 DecomposeGEPExpression(const Value *V, int64_t &BaseOffs, argument
297 BaseOffs = 0;
358 BaseOffs += DL->getStructLayout(STy)->getElementOffset(FieldNo);
365 BaseOffs += DL->getTypeAllocSize(*GTI)*CIdx->getSExtValue();
385 BaseOffs += IndexOffset.getSExtValue()*Scale;
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1913 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
1919 AM.BaseOffs%4 == 0;
1926 return isImmUs(AM.BaseOffs);
1929 return AM.Scale == 1 && AM.BaseOffs == 0;
1934 return isImmUs2(AM.BaseOffs);
1937 return AM.Scale == 2 && AM.BaseOffs == 0;
1941 return isImmUs4(AM.BaseOffs);
1944 return AM.Scale == 4 && AM.BaseOffs == 0;
/external/llvm/include/llvm/Target/
H A DTargetLowering.h1243 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1245 /// If BaseOffs is zero, there is no base offset.
1251 int64_t BaseOffs;
1254 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1634 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) {
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2561 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2570 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8749 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8761 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8766 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp6204 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6218 int64_t Offset = AM.BaseOffs;
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp361 if (!isInt<20>(AM.BaseOffs))
/external/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp7561 AM.BaseOffs = Offset->getSExtValue();
7569 AM.BaseOffs = -Offset->getSExtValue();
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp9934 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
9950 if (AM.BaseOffs)
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp16653 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
16671 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))

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