Searched refs:SubReg (Results 1 - 21 of 21) sorted by relevance

/external/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp100 static bool isGPR64(unsigned Reg, unsigned SubReg, argument
102 if (SubReg)
109 static bool isFPR64(unsigned Reg, unsigned SubReg, argument
113 SubReg == 0) ||
115 SubReg == AArch64::dsub);
117 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
118 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub);
125 unsigned &SubReg) {
126 SubReg = 0;
134 SubReg
123 getSrcFromCopy(const MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &SubReg) argument
235 unsigned SubReg; local
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H A DAArch64ISelDAGToDAG.cpp526 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32);
528 SDLoc(N), MVT::i32, N, SubReg);
665 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32); local
670 TargetOpcode::INSERT_SUBREG, SDLoc(N), MVT::i64, ImpDef, N, SubReg);
975 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32); local
979 CurDAG->getTargetConstant(0, MVT::i64), LoadedVal, SubReg),
1544 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32); local
1547 SDValue(BFM, 0), SubReg);
2106 unsigned SubReg; local
2114 SubReg
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H A DAArch64InstrInfo.cpp1285 int SubReg = 0, End = NumRegs, Incr = 1;
1287 SubReg = NumRegs - 1;
1292 for (; SubReg != End; SubReg += Incr) {
1294 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
1295 AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI);
1296 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
H A DAArch64ISelLowering.cpp6645 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32); local
6647 Source, SubReg),
/external/llvm/lib/CodeGen/
H A DLiveVariables.cpp198 unsigned SubReg = *SubRegs; local
199 MachineInstr *Def = PhysRegDef[SubReg];
204 LastDefReg = SubReg;
252 unsigned SubReg = *SubRegs; local
253 if (Processed.count(SubReg))
255 if (PartDefRegs.count(SubReg))
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
262 PhysRegDef[SubReg] = LastPartialDef;
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
291 unsigned SubReg local
340 unsigned SubReg = *SubRegs; local
371 unsigned SubReg = *SubRegs; local
453 unsigned SubReg = *SubRegs; local
475 unsigned SubReg = *SubRegs; local
493 unsigned SubReg = *SubRegs; local
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H A DMachineInstrBundle.cpp175 unsigned SubReg = *SubRegs; local
176 if (LocalDefSet.insert(SubReg))
177 LocalDefs.push_back(SubReg);
/external/llvm/lib/MC/
H A DMCRegisterInfo.cpp38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
39 assert(SubReg && SubReg < getNumRegs() && "This is not a register");
44 if (*Subs == SubReg)
/external/llvm/lib/Target/R600/
H A DSIFixSGPRCopies.cpp90 unsigned SubReg) const;
94 unsigned SubReg) const;
137 unsigned SubReg) const {
144 RC = TRI->getSubRegClass(RC, SubReg);
163 unsigned SubReg) const {
166 return TRI->getSubRegClass(RC, SubReg);
170 return TRI->getSubRegClass(MRI.getRegClass(Reg), SubReg);
H A DSILowerControlFlow.cpp407 unsigned SubReg = TRI->getSubReg(Vec, AMDGPU::sub0); local
408 if (!SubReg)
409 SubReg = Vec;
413 .addReg(SubReg + Off)
428 unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0); local
429 if (!SubReg)
430 SubReg = Dst;
434 .addReg(SubReg + Off, RegState::Define)
H A DR600OptimizeVectorRegisters.cpp191 unsigned SubReg = (*It).first; local
198 .addReg(SubReg)
200 UpdatedRegToChan[SubReg] = Chan;
H A DSIInstrInfo.cpp328 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(1).getReg(), local
334 .addReg(SubReg)
352 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(0).getReg(), local
356 BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), SubReg)
396 unsigned SubReg = MI->getOperand(1).getSubReg(); local
399 MI->getOperand(2).setSubReg(SubReg);
788 unsigned SubReg = MRI.createVirtualRegister(SubRC); local
799 SubReg)
801 return SubReg;
821 unsigned SubReg local
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/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h837 unsigned SubReg;
848 SubReg(0),
859 unsigned getSubReg() const { return SubReg; }
869 SubReg = *Idx++;
870 if (!SubReg)
/external/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp108 // SubReg of Reg.
109 static bool resultTests(MachineInstr *MI, unsigned Reg, unsigned SubReg) { argument
114 MI->getOperand(0).getSubReg() == SubReg)
131 MI->getOperand(1).getSubReg() == SubReg)
H A DSystemZISelLowering.h303 bool ClearEven, unsigned SubReg) const;
H A DSystemZISelLowering.cpp3080 // it's "don't care". SubReg is subreg_l32 when extending a GR32
3085 bool ClearEven, unsigned SubReg) const {
3108 .addReg(In128).addReg(Src).addImm(SubReg);
/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h65 unsigned SubReg = 0) const {
75 SubReg,
H A DMachineOperand.h347 assert(SubReg_TargetFlags == subReg && "SubReg out of range");
351 /// subregister Reg:SubReg. Take any existing SubReg index into account,
358 /// Reg, taking any existing SubReg into account. For instance,
580 unsigned SubReg = 0,
598 Op.setSubReg(SubReg);
/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp522 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
536 BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg).addReg(
539 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp619 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
620 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
/external/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp347 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? local
349 O << ARMInstPrinter::getRegisterName(SubReg);
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp311 // Compute the inverse SubReg -> Idx map.
429 const CodeGenRegister *SubReg = I->second; local
430 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs;
506 // Topological signature computed from SubIdx, TopoId(SubReg).

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