/external/llvm/include/llvm/CodeGen/ |
H A D | MachineOperand.h | 191 return isReg() ? 0 : SubReg_TargetFlags; 194 assert(!isReg() && "Register operands can't have target flags"); 199 assert(!isReg() && "Register operands can't have target flags"); 226 /// isReg - Tests if this is a MO_Register operand. 227 bool isReg() const { return OpKind == MO_Register; } function in class:llvm::MachineOperand 265 assert(isReg() && "This is not a register operand!"); 270 assert(isReg() && "Wrong MachineOperand accessor"); 275 assert(isReg() && "Wrong MachineOperand accessor"); 280 assert(isReg() && "Wrong MachineOperand accessor"); 285 assert(isReg() [all...] |
H A D | LiveVariables.h | 215 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) { 251 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
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/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) { function 33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); 191 if (Op.isReg()) { 276 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && 278 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS)); 281 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); 284 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); 287 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); 290 return isReg<Mip [all...] |
/external/llvm/lib/CodeGen/ |
H A D | LivePhysRegs.cpp | 39 if (O->isReg()) { 52 if (!O->isReg() || !O->readsReg() || O->isUndef()) 69 if (O->isReg()) {
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H A D | AntiDepBreaker.h | 64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
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H A D | DeadMachineInstructionElim.cpp | 69 if (MO.isReg() && MO.isDef()) { 129 if (!MO.isReg() || !MO.isDef()) 148 if (MO.isReg() && MO.isDef()) { 167 if (MO.isReg() && MO.isUse()) {
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H A D | MachineInstr.cpp | 91 assert(isReg() && "Wrong MachineOperand accessor"); 112 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); 115 if (isReg() && isOnRegUseList()) 138 bool WasReg = isReg(); 597 if (Operands[i].isReg()) 606 if (Operands[i].isReg()) 659 bool isImpReg = Op.isReg() && Op.isImplicit(); 661 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { 706 if (NewMO->isReg()) { 741 if (Operands[i].isReg()) [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 18 if (Op.isReg()) {
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/external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 18 if (Op.isReg()) {
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/external/llvm/include/llvm/MC/MCParser/ |
H A D | MCParsedAsmOperand.h | 47 /// isReg - Is this a register operand? 48 virtual bool isReg() const = 0;
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/external/llvm/lib/Target/Sparc/InstPrinter/ |
H A D | SparcInstPrinter.cpp | 62 if (!MI->getOperand(0).isReg()) 86 || (!MI->getOperand(0).isReg()) 112 if (MO.isReg()) { 139 if (MO.isReg() && MO.getReg() == SP::G0)
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 252 bool isReg() const { return Kind == CV_Register; } function in class:__anon26012::CountValue 256 assert(isReg() && "Wrong CountValue accessor"); 260 assert(isReg() && "Wrong CountValue accessor"); 270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); } 527 if (Op1.isReg()) { 564 if (InitialValue->isReg()) { 591 if (InitialValue->isReg()) { 598 if (EndValue->isReg()) { 624 if (Start->isReg()) { 629 if (End->isReg()) { [all...] |
H A D | HexagonAsmPrinter.cpp | 127 if (!MI->getOperand(OpNo).isReg() || 129 !MI->getOperand(OpNo+1).isReg()) 156 if (Base.isReg())
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H A D | HexagonNewValueJump.cpp | 149 if (II->getOperand(i).isReg() && 473 MI->getOperand(0).isReg() && 481 isSecondOpReg = MI->getOperand(2).isReg(); 515 if (MI->getOperand(0).isReg() && 572 if (MO.isReg() && MO.isUse()) { 579 if (localMO.isReg() && localMO.isUse() && 634 if (cmpInstr->getOperand(0).isReg() && 637 if (cmpInstr->getOperand(1).isReg() &&
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H A D | HexagonVLIWPacketizer.cpp | 357 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) { 484 if (MI->getOperand(opNum).isReg() && 490 if (MI->getOperand(opNum).isReg() && 499 assert(MI->getOperand(1).isReg() && 505 assert(MI->getOperand(0).isReg() && 548 if (GetStoreValueOperand(MI).isReg() && 612 if ( PacketMI->getOperand(opNum).isReg()) 624 if ( MI->getOperand(opNum).isReg()) 678 if (MI->getOperand(opNum).isReg() && 692 GetStoreValueOperand(MI).isReg() [all...] |
H A D | HexagonCopyToCombine.cpp | 119 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isReg()); 130 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm()); 141 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isGlobal()); 213 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill()) 370 if (!Op.isReg() || !Op.isUse() || !Op.getReg()) 400 if (!Op.isReg() || !Op.isDef() || !Op.getReg()) 539 bool IsHiReg = HiOperand.isReg(); 540 bool IsLoReg = LoOperand.isReg();
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 167 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 179 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 192 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 205 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 217 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 230 assert(MI.getOperand(OpNo+1).isReg()); 249 assert(MI.getOperand(OpNo+1).isReg()); 267 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); 307 if (MO.isReg()) {
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCCodeEmitter.cpp | 118 if (MO.isReg()) 145 if (MO.isReg() || MO.isImm()) 180 if (MO.isReg() || MO.isImm()) 193 if (MO.isReg() || MO.isImm()) 205 if (MO.isReg() || MO.isImm())
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/external/llvm/include/llvm/MC/ |
H A D | MCInst.h | 56 bool isReg() const { return Kind == kRegister; } function in class:llvm::MCOperand 64 assert(isReg() && "This is not a register operand!"); 70 assert(isReg() && "This is not a register operand!");
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H A D | MachineLocation.h | 53 bool isReg() const { return IsRegister; } function
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCCodeEmitter.cpp | 190 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 206 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 219 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 236 assert(MI.getOperand(OpNo+1).isReg()); 252 assert(MI.getOperand(OpNo+1).isReg()); 279 if (MO.isReg()) {
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64DeadRegisterDefinitionsPass.cpp | 54 if (MO.isReg() && MO.isDef()) 80 if (MO.isReg() && MO.isDead() && MO.isDef()) {
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H A D | AArch64AsmPrinter.cpp | 166 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm()) 254 assert(MO.isReg() && "Should only get here with a register!"); 284 if (MO.isReg()) 298 if (MO.isReg()) { 328 if (MO.isReg()) { 354 assert(MO.isReg() && "unexpected inline asm memory operand"); 369 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
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/external/llvm/lib/MC/ |
H A D | MCInst.cpp | 22 else if (isReg())
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/external/llvm/lib/Target/XCore/InstPrinter/ |
H A D | XCoreInstPrinter.cpp | 75 if (Op.isReg()) {
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