Searched refs:isReg (Results 1 - 25 of 180) sorted by last modified time

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/external/valgrind/main/VEX/priv/
H A Dguest_amd64_toIR.c7045 Bool isReg = epartIsReg(modrm); local
7138 if (isReg) {
7176 ( isReg ? nameMMXReg(eregLO3ofRM(modrm)) : dis_buf ),
8121 Bool isReg; local
8135 isReg = epartIsReg(modrm);
8136 if (isReg) {
8148 ( isReg ? nameIRegE(sz, pfx, modrm) : dis_buf ),
[all...]
H A Dguest_x86_toIR.c5562 Bool isReg = epartIsReg(modrm); local
5655 if (isReg) {
5693 ( isReg ? nameMMXReg(eregOfRM(modrm)) : dis_buf ),
6460 Bool isReg; local
6476 isReg = epartIsReg(modrm);
6477 if (isReg) {
6489 ( isReg ? nameIReg(sz, eregOfRM(modrm)) : dis_buf ),
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUAsmPrinter.cpp76 if (!MO.isReg()) {
H A DAMDGPUInstrInfo.cpp247 if (MO.isReg() && MO.isDef()) {
/external/mesa3d/src/gallium/drivers/radeon/InstPrinter/
H A DAMDGPUInstPrinter.cpp18 if (Op.isReg()) {
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DR600MCCodeEmitter.cpp245 if (MO.isReg()) {
264 if (MO.isReg()) {
273 (MO.isReg() &&
301 if (MO.isReg() && MO.getReg() != AMDGPU::PREDICATE_BIT) {
623 if (MO.isReg()) {
H A DSIMCCodeEmitter.cpp143 if (MO.isReg()) {
235 if (MO.isReg()) {
/external/llvm/utils/TableGen/
H A DCodeGenInstruction.h321 bool isReg() const { return Kind == K_Reg; } function in struct:llvm::CodeGenInstAlias::ResultOperand
326 Record *getRegister() const { assert(isReg()); return R; }
H A DFastISelEmitter.cpp94 bool isReg() const { return Repr == OK_Reg; }
102 if (isReg())
285 if (Operands[i].isReg()) {
310 if (Operands[i].isReg()) {
327 if (Operands[i].isReg()) {
H A DFixedLenDecoderEmitter.cpp1855 bool isReg = false;
1860 isReg = true;
1864 isReg = true;
1870 if (!isReg && String && String->getValue() != "")
1927 bool isReg = false;
1932 isReg = true;
1936 isReg = true;
1942 if (!isReg && String && String->getValue() != "")
/external/llvm/include/llvm/CodeGen/
H A DLiveVariables.h215 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
251 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
H A DMachineInstr.h698 && getOperand(0).isReg()
944 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
957 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1112 if (MO.isReg() && MO.isTied()) {
H A DMachineOperand.h191 return isReg() ? 0 : SubReg_TargetFlags;
194 assert(!isReg() && "Register operands can't have target flags");
199 assert(!isReg() && "Register operands can't have target flags");
226 /// isReg - Tests if this is a MO_Register operand.
227 bool isReg() const { return OpKind == MO_Register; } function in class:llvm::MachineOperand
265 assert(isReg() && "This is not a register operand!");
270 assert(isReg() && "Wrong MachineOperand accessor");
275 assert(isReg() && "Wrong MachineOperand accessor");
280 assert(isReg() && "Wrong MachineOperand accessor");
285 assert(isReg()
[all...]
H A DMachineRegisterInfo.h90 assert(MO && MO->isReg() && "This is not a register operand!");
/external/llvm/include/llvm/MC/
H A DMCInst.h56 bool isReg() const { return Kind == kRegister; } function in class:llvm::MCOperand
64 assert(isReg() && "This is not a register operand!");
70 assert(isReg() && "This is not a register operand!");
H A DMCInstrDesc.h299 if (MI.getOperand(i).isReg() &&
566 if (MI.getOperand(i).isReg() &&
H A DMachineLocation.h53 bool isReg() const { return IsRegister; } function
/external/llvm/include/llvm/MC/MCParser/
H A DMCParsedAsmOperand.h47 /// isReg - Is this a register operand?
48 virtual bool isReg() const = 0;
/external/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp227 if (!MO.isReg() || !MO.isImplicit())
247 if (!MO.isReg()) continue;
349 if (!MO.isReg() || !MO.isDef()) continue;
359 if (!MO.isReg() || !MO.isDef()) continue;
399 if (!MO.isReg() || !MO.isDef()) continue;
452 if (!MO.isReg() || !MO.isUse()) continue;
487 if (!MO.isReg()) continue;
H A DAntiDepBreaker.h64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
/external/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinter.cpp617 assert(Op.isReg() && "KILL instruction must have only register operands");
647 bool Deref = MI->getOperand(0).isReg() && MI->getOperand(1).isImm();
671 if (MI->getOperand(0).isReg()) {
H A DAsmPrinterDwarf.cpp251 assert(MLoc.isReg() && "MLoc must be a register");
H A DAsmPrinterInlineAsm.cpp436 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
H A DDbgValueHistoryCalculator.cpp32 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : 0;
119 if (!MO.isReg() || !MO.isDef() || !MO.getReg())
H A DDwarfDebug.cpp1169 if (MI->getOperand(0).isReg()) {
1248 if (Begin->getNumOperands() > 1 && Begin->getOperand(0).isReg() &&
2005 if (!Loc.isReg())

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