Searched refs:MI (Results 101 - 125 of 514) sorted by relevance

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/external/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp97 MachineInstr &MI,
106 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
107 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
120 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
125 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
128 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
129 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset));
138 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
140 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
143 BuildMI(*MI
95 replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II, MachineInstr &MI, DebugLoc dl, unsigned FIOperandNum, int Offset, unsigned FramePtr) argument
157 MachineInstr &MI = *II; local
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/external/llvm/lib/Target/XCore/
H A DXCoreAsmPrinter.cpp66 void printInlineJT(const MachineInstr *MI, int opNum, raw_ostream &O,
68 void printInlineJT32(const MachineInstr *MI, int opNum, raw_ostream &O) { argument
69 printInlineJT(MI, opNum, O, ".jmptable32");
71 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
72 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
75 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
83 void EmitInstruction(const MachineInstr *MI) override;
195 printInlineJT(const MachineInstr *MI, int opNum, raw_ostream &O, argument
197 unsigned JTI = MI->getOperand(opNum).getIndex();
198 const MachineFunction *MF = MI
211 printOperand(const MachineInstr *MI, int opNum, raw_ostream &O) argument
242 PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant,const char *ExtraCode, raw_ostream &O) argument
256 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
269 EmitInstruction(const MachineInstr *MI) argument
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/external/llvm/lib/Target/ARM/
H A DARMAsmPrinter.h59 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
62 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
65 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
72 void EmitJumpTable(const MachineInstr *MI);
73 void EmitJump2Table(const MachineInstr *MI);
74 void EmitInstruction(const MachineInstr *MI) override;
94 void EmitPatchedInstruction(const MachineInstr *MI, unsigned TargetOpc);
96 void EmitUnwindingInstruction(const MachineInstr *MI);
100 const MachineInstr *MI);
H A DThumb2ITBlockPass.cpp44 bool MoveCopyOutOfITBlock(MachineInstr *MI,
56 static void TrackDefUses(MachineInstr *MI, argument
63 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
64 MachineOperand &MO = MI->getOperand(i);
93 static bool isCopy(MachineInstr *MI) { argument
94 switch (MI->getOpcode()) {
106 Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI, argument
110 if (!isCopy(MI))
115 assert(MI->getOperand(0).getSubReg() == 0 &&
116 MI
169 MachineInstr *MI = &*MBBI; local
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/external/llvm/lib/CodeGen/
H A DMachineLICM.cpp154 MachineInstr *MI; member in struct:__anon25767::MachineLICM::CandidateInfo
158 : MI(mi), Def(def), FI(fi) {}
168 void HoistPostRA(MachineInstr *MI, unsigned Def);
172 void ProcessMI(MachineInstr *MI,
196 bool HasLoopPHIUse(const MachineInstr *MI) const;
201 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
204 bool IsCheapInstruction(MachineInstr &MI) const;
213 /// effect of hoisting MI from the current block to the preheader.
214 void UpdateBackTraceRegPressure(const MachineInstr *MI);
218 bool IsProfitableToHoist(MachineInstr &MI);
391 InstructionStoresToFI(const MachineInstr *MI, int FI) argument
407 ProcessMI(MachineInstr *MI, BitVector &PhysRegDefs, BitVector &PhysRegClobbers, SmallSet<int, 32> &StoredFIs, SmallVectorImpl<CandidateInfo> &Candidates) argument
531 MachineInstr *MI = &*MII; local
568 MachineInstr *MI = Candidates[i].MI; local
598 MachineInstr *MI = &*MII; local
612 HoistPostRA(MachineInstr *MI, unsigned Def) argument
765 MachineInstr *MI = &*MII; local
783 getRegisterClassIDAndCost(const MachineInstr *MI, unsigned Reg, unsigned OpIdx, unsigned &RCId, unsigned &RCCost) const argument
816 MachineInstr *MI = &*MII; local
844 UpdateRegPressure(const MachineInstr *MI) argument
882 isLoadFromGOTOrConstantPool(MachineInstr &MI) argument
1010 HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, unsigned Reg) const argument
1098 UpdateBackTraceRegPressure(const MachineInstr *MI) argument
1143 IsProfitableToHoist(MachineInstr &MI) argument
1241 ExtractHoistableLoad(MachineInstr *MI) argument
1300 const MachineInstr *MI = &*I; local
1315 LookForDuplicate(const MachineInstr *MI, std::vector<const MachineInstr*> &PrevMIs) argument
1325 EliminateCSE(MachineInstr *MI, DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) argument
1384 MayCSE(MachineInstr *MI) argument
1399 Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) argument
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H A DRegAllocFast.cpp166 void handleThroughOperands(MachineInstr *MI,
174 void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator);
175 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
178 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
188 LiveRegMap::iterator allocVirtReg(MachineInstr *MI, LiveRegMap::iterator,
190 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
192 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
194 void spillAll(MachineBasicBlock::iterator MI);
195 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
267 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigne argument
276 spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator LRI) argument
329 spillAll(MachineBasicBlock::iterator MI) argument
400 definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState) argument
508 allocVirtReg(MachineInstr *MI, LiveRegMap::iterator LRI, unsigned Hint) argument
583 defineVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument
616 reloadVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument
667 setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) argument
696 handleThroughOperands(MachineInstr *MI, SmallVectorImpl<unsigned> &VirtDead) argument
805 MachineInstr *MI = MII++; local
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H A DDeadMachineInstructionElim.cpp45 bool isDead(const MachineInstr *MI) const;
54 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
58 if (MI->isInlineAsm())
63 if (!MI->isSafeToMove(TII, nullptr, SawStore) && !MI->isPHI())
67 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
68 const MachineOperand &MO = MI->getOperand(i);
119 MachineInstr *MI = &*MII; local
122 if (isDead(MI)) {
123 DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIInstrInfo.h34 MachineBasicBlock::iterator MI, DebugLoc DL,
39 unsigned getEncodingType(const MachineInstr &MI) const;
43 unsigned getEncodingBytes(const MachineInstr &MI) const;
H A DAMDGPUMCInstLower.h24 void lower(const MachineInstr *MI, MCInst &OutMI) const;
/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.h41 EmitInstrWithCustomInserter(MachineInstr *MI,
78 MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
80 MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
84 MachineBasicBlock *emitCOPY_FW(MachineInstr *MI,
87 MachineBasicBlock *emitCOPY_FD(MachineInstr *MI,
90 MachineBasicBlock *emitINSERT_FW(MachineInstr *MI,
93 MachineBasicBlock *emitINSERT_FD(MachineInstr *MI,
96 MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI,
101 MachineBasicBlock *emitFILL_FW(MachineInstr *MI,
104 MachineBasicBlock *emitFILL_FD(MachineInstr *MI,
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H A DMipsMCInstLower.h34 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
42 void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
43 void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
46 bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
H A DMips16RegisterInfo.cpp84 MachineInstr &MI = *II; local
85 MachineFunction &MF = *MI.getParent()->getParent();
114 if ((MI.getNumOperands()> OpNo+2) && MI.getOperand(OpNo+2).isReg())
115 FrameReg = MI.getOperand(OpNo+2).getReg();
132 Offset += MI.getOperand(OpNo + 1).getImm();
137 if (!MI.isDebugValue() &&
138 !Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)) {
139 MachineBasicBlock &MBB = *MI.getParent();
149 MI
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/external/llvm/lib/Target/R600/
H A DR600InstrInfo.h37 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
65 MachineBasicBlock::iterator MI, DebugLoc DL,
71 bool isTrig(const MachineInstr &MI) const;
85 bool canBeConsideredALU(const MachineInstr *MI) const;
88 bool isTransOnly(const MachineInstr *MI) const;
90 bool isVectorOnly(const MachineInstr *MI) const;
94 bool usesVertexCache(const MachineInstr *MI) const;
96 bool usesTextureCache(const MachineInstr *MI) const;
99 bool usesAddressRegister(MachineInstr *MI) const;
100 bool definesAddressRegister(MachineInstr *MI) cons
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H A DR600Packetizer.cpp66 unsigned getSlot(const MachineInstr *MI) const {
67 return TRI.getHWRegChan(MI->getOperand(0).getReg());
132 void substitutePV(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PVs) argument
140 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
143 unsigned Src = MI->getOperand(OperandIdx).getReg();
146 MI->getOperand(OperandIdx).setReg(It->second);
165 bool ignorePseudoInstruction(MachineInstr *MI,
170 // isSoloInstruction - return true if instruction MI can not be packetized
171 // with any other instruction, which means that MI itself is a packet.
172 bool isSoloInstruction(MachineInstr *MI) overrid
229 setIsLastBit(MachineInstr *MI, unsigned Bit) const argument
234 isBundlableWithCurrentPMI(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, std::vector<R600InstrInfo::BankSwizzle> &BS, bool &isTransSlot) argument
306 MachineInstr *MI = CurrentPacketMIs[i]; variable
354 MachineBasicBlock::iterator MI = MBB->begin(); local
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H A DR600ClauseMergePass.cpp33 static bool isCFAlu(const MachineInstr *MI) { argument
34 switch (MI->getOpcode()) {
49 unsigned getCFAluSize(const MachineInstr *MI) const;
50 bool isCFAluEnabled(const MachineInstr *MI) const;
73 unsigned R600ClauseMergePass::getCFAluSize(const MachineInstr *MI) const {
74 assert(isCFAlu(MI));
75 return MI->getOperand(
76 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::COUNT)).getImm();
79 bool R600ClauseMergePass::isCFAluEnabled(const MachineInstr *MI) const {
80 assert(isCFAlu(MI));
177 MachineInstr *MI = I++; local
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/external/mesa3d/src/gallium/drivers/radeon/
H A DSIInstrInfo.h34 MachineBasicBlock::iterator MI, DebugLoc DL,
39 unsigned getEncodingType(const MachineInstr &MI) const;
43 unsigned getEncodingBytes(const MachineInstr &MI) const;
H A DAMDGPUMCInstLower.h24 void lower(const MachineInstr *MI, MCInst &OutMI) const;
/external/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp134 // feeder insn between it's definition, this MI and jump, jmpInst
223 MachineInstr *MI = II; local
228 int64_t v = MI->getOperand(2).getImm();
231 ((MI->getOpcode() == Hexagon::CMPEQri ||
232 MI->getOpcode() == Hexagon::CMPGTri) &&
238 cmpReg1 = MI->getOperand(1).getReg();
241 cmpOp2 = MI->getOperand(2).getReg();
286 // compare operator. Make sure that MI here is included in
288 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, argument
294 MachineBasicBlock *Src = MI
405 MachineInstr *MI = --MII; local
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H A DHexagonAsmPrinter.h40 void EmitInstruction(const MachineInstr *MI) override;
42 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
43 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
46 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
H A DHexagonInstrInfo.cpp75 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, argument
79 switch (MI->getOpcode()) {
86 if (MI->getOperand(2).isFI() &&
87 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
88 FrameIndex = MI->getOperand(2).getIndex();
89 return MI->getOperand(0).getReg();
102 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI, argument
104 switch (MI->getOpcode()) {
110 if (MI
342 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
558 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI, const SmallVectorImpl<unsigned> &Ops, int FI) const argument
805 PredicateInstruction(MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Cond) const argument
1036 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument
1581 GetDotNewPredOp(MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const argument
1646 isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const argument
1716 getDotNewPredJumpOp(MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const argument
1741 isOperandExtended(const MachineInstr *MI, unsigned short OperandNum) const argument
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/external/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCCodeEmitter.cpp43 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
49 uint64_t getBinaryCodeForInstr(const MCInst &MI,
55 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
59 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
62 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
65 unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
68 unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
83 EncodeInstruction(const MCInst &MI, raw_ostream &OS, argument
86 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
94 switch (MI
114 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
141 getCallTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
176 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
189 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
201 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
H A DR600MCCodeEmitter.cpp53 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
57 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
61 void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
63 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
64 void EmitDst(const MCInst &MI, raw_ostream &OS) const;
65 void EmitALU(const MCInst &MI, unsigned numSrc,
68 void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
70 void EmitFCInstr(const MCInst &MI, raw_ostream &OS) const;
87 bool isFlagSet(const MCInst &MI, unsigned Operand, unsigned Flag) const;
150 void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostrea argument
192 EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument
234 EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const argument
298 EmitDst(const MCInst &MI, raw_ostream &OS) const argument
330 EmitALU(const MCInst &MI, unsigned numSrc, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument
393 EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument
485 EmitFCInstr(const MCInst &MI, raw_ostream &OS) const argument
620 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixup) const argument
674 isFlagSet(const MCInst &MI, unsigned Operand, unsigned Flag) const argument
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DR600MCCodeEmitter.cpp53 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
57 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
61 void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
63 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
64 void EmitDst(const MCInst &MI, raw_ostream &OS) const;
65 void EmitALU(const MCInst &MI, unsigned numSrc,
68 void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
70 void EmitFCInstr(const MCInst &MI, raw_ostream &OS) const;
87 bool isFlagSet(const MCInst &MI, unsigned Operand, unsigned Flag) const;
150 void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostrea argument
192 EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument
234 EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const argument
298 EmitDst(const MCInst &MI, raw_ostream &OS) const argument
330 EmitALU(const MCInst &MI, unsigned numSrc, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument
393 EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument
485 EmitFCInstr(const MCInst &MI, raw_ostream &OS) const argument
620 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixup) const argument
674 isFlagSet(const MCInst &MI, unsigned Operand, unsigned Flag) const argument
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/external/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp101 MachineInstr *MI = MBBI; local
103 switch (MI->getOpcode()) {
106 const MachineOperand &Src = MI->getOperand(1);
107 const MachineOperand &Dest = MI->getOperand(0);
108 NewMI = BuildMI(*MF, MI->getDebugLoc(),
109 TII->get(MI->getOpcode() == X86::MOV32rr ? X86::LEA32r
132 if (!MI->getOperand(2).isImm()) {
140 if (MI->getOperand(1).getReg() != MI->getOperand(2).getReg()) {
173 MachineInstr *MI local
230 MachineInstr *MI = I; local
268 MachineInstr *MI = I; local
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/external/llvm/lib/Target/AArch64/
H A DAArch64A53Fix835769.cpp41 static bool isFirstInstructionInSequence(MachineInstr *MI) { argument
43 switch (MI->getOpcode()) {
51 return (MI->mayLoad() || MI->mayStore());
57 static bool isSecondInstructionInSequence(MachineInstr *MI) { argument
60 switch (MI->getOpcode()) {
71 return MI->getOperand(3).getReg() != AArch64::XZR;
168 static void insertNopBeforeInstruction(MachineBasicBlock &MBB, MachineInstr* MI, argument
172 if (MI == &MBB.front()) {
179 DebugLoc DL = MI
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