Searched refs:STI (Results 126 - 150 of 166) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp138 const ARMSubtarget *STI; member in class:__anon26006::Thumb2SizeReduce
250 if (MinimizeSize || !STI->avoidCPSRPartialUpdate())
636 STI->avoidMOVsShifterOperand())
753 STI->avoidMOVsShifterOperand())
1007 STI = &TM.getSubtarget<ARMSubtarget>();
H A DThumb2InstrInfo.cpp32 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI) argument
33 : ARMBaseInstrInfo(STI), RI(STI) {
H A DARMBaseInstrInfo.h35 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
53 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
H A DARMLoadStoreOptimizer.cpp70 const ARMSubtarget *STI; member in struct:__anon25980::ARMLoadStoreOpt
757 (!STI->isSwift() || isNotVFP || Count != 1 || !(PRegNum & 0x1))) {
1396 bool Errata602117 = EvenReg == BaseReg && STI->isCortexM3();
1732 STI = &TM.getSubtarget<ARMSubtarget>();
1769 const ARMSubtarget *STI; member in struct:__anon25981::ARMPreAllocLoadStoreOpt
1799 STI = &Fn.getTarget().getSubtarget<ARMSubtarget>();
1883 if (!STI->hasV5TEOps())
1914 unsigned ReqAlign = STI->hasV6Ops()
/external/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp37 MCSubtargetInfo &STI; member in class:__anon26131::SparcAsmParser
79 bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); }
84 : MCTargetAsmParser(), STI(sti), Parser(parser) {
86 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
401 Out.EmitInstruction(Inst, STI);
/external/clang/lib/Parse/
H A DParseStmtAsm.cpp485 std::unique_ptr<llvm::MCSubtargetInfo> STI(
503 TheTarget->createMCAsmParser(*STI, *Parser, *MII, MCOptions));
506 TheTarget->createMCInstPrinter(1, *MAI, *MII, *MRI, *STI));
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp57 MCSubtargetInfo &STI; member in class:__anon26165::X86AsmParser
712 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
716 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
720 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
723 uint64_t oldMode = STI.getFeatureBits() &
725 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(oldMode | mode));
727 assert(mode == (STI.getFeatureBits() &
747 : MCTargetAsmParser(), STI(sti), Parser(parser), MII(mii),
751 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
753 CreateX86AsmInstrumentation(Options, Parser.getContext(), STI));
[all...]
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp355 const MCSubtargetInfo &STI,
377 const MCSubtargetInfo &STI) {
351 createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) argument
372 createX86MCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp93 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : argument
94 MCDisassembler(STI, Ctx) {
112 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : argument
113 MCDisassembler(STI, Ctx) {
404 const MCSubtargetInfo &STI,
406 return new ARMDisassembler(STI, Ctx);
410 const MCSubtargetInfo &STI,
412 return new ThumbDisassembler(STI, Ctx);
424 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
441 Address, this, STI);
403 createARMDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
409 createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h40 explicit AArch64InstrInfo(const AArch64Subtarget &STI);
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAsmBackend.cpp43 const MCSubtargetInfo* STI; member in class:__anon25992::ARMAsmBackend
48 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
52 delete STI;
60 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
/external/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp298 MCSubtargetInfo &STI; member in class:__anon26144::SystemZAsmParser
334 : MCTargetAsmParser(), STI(sti), Parser(parser) {
338 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
691 Out.EmitInstruction(Inst, STI);
/external/llvm/tools/llvm-objdump/
H A Dllvm-objdump.cpp305 std::unique_ptr<const MCSubtargetInfo> STI(
307 if (!STI) {
322 TheTarget->createMCDisassembler(*STI, Ctx));
347 AsmPrinterVariant, *AsmInfo, *MII, *MRI, *STI));
/external/llvm/lib/MC/
H A DMCAsmStreamer.cpp230 void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
1174 const MCSubtargetInfo &STI) {
1179 Emitter->EncodeInstruction(Inst, VecOS, Fixups, STI);
1258 void MCAsmStreamer::EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) {
1264 AddEncodingComment(Inst, STI);
1173 AddEncodingComment(const MCInst &Inst, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp38 const MCSubtargetInfo &STI)
41 setAvailableFeatures(STI.getFeatureBits());
47 const MCSubtargetInfo &STI)
48 : AArch64InstPrinter(MAI, MII, MRI, STI) {}
35 AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
44 AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.h27 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
/external/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp33 MSP430InstrInfo::MSP430InstrInfo(MSP430Subtarget &STI) argument
/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp45 RI(), STI(sti) {
508 if (STI.hasLoadStoreOnCond() &&
540 if (STI.hasLoadStoreOnCond()) {
688 if (STI.hasDistinctOps()) {
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.h169 explicit X86InstrInfo(X86Subtarget &STI);
/external/llvm/include/llvm/MC/
H A DMCAssembler.h296 /// STI - The MCSubtargetInfo in effect when the instruction was encoded.
297 /// Keep a copy instead of a reference to make sure that updates to STI
299 const MCSubtargetInfo STI; member in class:llvm::MCRelaxableFragment
311 : MCEncodedFragmentWithFixups(FT_Relaxable, SD), Inst(_Inst), STI(_STI) {
320 const MCSubtargetInfo &getSubtargetInfo() { return STI; }
H A DMCStreamer.h719 virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI);
/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp197 const MCSubtargetInfo &STI,
199 return new AArch64Disassembler(STI, Ctx);
222 return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
635 const MCSubtargetInfo &STI = Dis->getSubtargetInfo(); local
641 (void)AArch64SysReg::MRSMapper(STI.getFeatureBits())
652 const MCSubtargetInfo &STI = Dis->getSubtargetInfo(); local
658 (void)AArch64SysReg::MSRMapper(STI.getFeatureBits())
196 createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp64 PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI) argument
66 Subtarget(STI), RI(STI) {}
71 PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, argument
74 static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
78 &static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
82 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
H A DPPCFrameLowering.cpp39 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI) argument
41 (STI.hasQPX() || STI.isBGQ()) ? 32 : 16, 0),
42 Subtarget(STI) {}
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h756 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,

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