Searched defs:Reg (Results 76 - 100 of 253) sorted by path

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/external/llvm/lib/CodeGen/
H A DRegisterPressure.cpp151 const LiveRange *RegPressureTracker::getLiveRange(unsigned Reg) const {
152 if (TargetRegisterInfo::isVirtualRegister(Reg))
153 return &LIS->getInterval(Reg);
154 return LIS->getCachedRegUnit(Reg);
294 unsigned Reg = P.LiveOutRegs[i]; local
295 if (TargetRegisterInfo::isVirtualRegister(Reg)
296 && !RPTracker.hasUntiedDef(Reg)) {
297 increaseSetPressure(LiveThruPressure, MRI->getPressureSets(Reg));
343 void pushRegUnits(unsigned Reg, SmallVectorImpl<unsigned> &RegUnits) { argument
344 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
431 discoverLiveIn(unsigned Reg) argument
442 discoverLiveOut(unsigned Reg) argument
501 unsigned Reg = RegOpers.Defs[i]; local
526 unsigned Reg = RegOpers.Uses[i]; local
545 unsigned Reg = RegOpers.Defs[i]; local
581 unsigned Reg = RegOpers.Uses[i]; local
606 unsigned Reg = RegOpers.Defs[i]; local
721 unsigned Reg = RegOpers.Defs[i]; local
738 unsigned Reg = RegOpers.Uses[i]; local
882 findUseBetween(unsigned Reg, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo *MRI, const LiveIntervals *LIS) argument
919 unsigned Reg = RegOpers.Uses[i]; local
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H A DRegisterScavenging.cpp34 void RegScavenger::setUsed(unsigned Reg) { argument
35 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
40 bool RegScavenger::isAliasUsed(unsigned Reg) const {
41 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
42 if (isUsed(*AI, *AI == Reg))
50 I->Reg = 0;
107 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { argument
108 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
133 unsigned Reg = MO.getReg(); local
134 if (!Reg || TargetRegisterInf
205 unsigned Reg = MO.getReg(); local
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H A DScheduleDAGInstrs.cpp224 unsigned Reg = MO.getReg(); local
225 if (Reg == 0) continue;
227 if (TRI->isPhysicalRegister(Reg))
228 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
243 unsigned Reg = *I; local
244 if (!Uses.contains(Reg))
245 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
318 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
320 SDep Dep(SU, Kind, /*Reg=*/*Alias);
340 unsigned Reg local
378 unsigned Reg = MI->getOperand(OperIdx).getReg(); local
416 unsigned Reg = MI->getOperand(OperIdx).getReg(); local
817 unsigned Reg = MO.getReg(); local
1064 unsigned Reg = *I; local
1129 unsigned Reg = MO.getReg(); local
1148 unsigned Reg = MO.getReg(); local
1183 unsigned Reg = MO.getReg(); local
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H A DStackMaps.cpp89 unsigned Reg = (++MOI)->getReg(); local
91 Locs.push_back(Location(StackMaps::Location::Direct, Size, Reg, Imm));
97 unsigned Reg = (++MOI)->getReg(); local
99 Locs.push_back(Location(StackMaps::Location::Indirect, Size, Reg, Imm));
139 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) { argument
140 int RegNo = TRI->getDwarfRegNum(Reg, false);
141 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNo < 0; ++SR)
148 /// Create a live-out register record for the given register Reg.
150 StackMaps::createLiveOutReg(unsigned Reg, const TargetRegisterInfo *TRI) const { argument
151 unsigned RegNo = getDwarfRegNum(Reg, TR
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H A DTailDuplication.cpp343 static bool isDefLiveOut(unsigned Reg, MachineBasicBlock *BB, argument
345 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
437 unsigned Reg = MO.getReg(); local
438 if (!TargetRegisterInfo::isVirtualRegister(Reg))
441 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
444 LocalVRMap.insert(std::make_pair(Reg, NewReg));
445 if (isDefLiveOut(Reg, TailBB, MRI) || UsedByPhi.count(Reg))
446 AddSSAUpdateEntry(Reg, NewReg, PredBB);
448 DenseMap<unsigned, unsigned>::iterator VI = LocalVRMap.find(Reg);
484 unsigned Reg = MO0.getReg(); local
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H A DTargetInstrInfo.cpp608 unsigned Reg = MO.getReg(); local
609 if (Reg == 0)
613 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
618 if (!MRI.isConstantPhysReg(Reg, MF))
629 if (MO.isDef() && Reg != DefReg)
H A DTargetRegisterInfo.cpp37 if (!Reg)
39 else if (TargetRegisterInfo::isStackSlot(Reg))
40 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
41 else if (TargetRegisterInfo::isVirtualRegister(Reg))
42 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
43 else if (TRI && Reg < TRI->getNumRegs())
44 OS << '%' << TRI->getName(Reg);
46 OS << "%physreg" << Reg; local
H A DTargetSchedule.cpp269 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg(); local
272 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
H A DTwoAddressInstructionPass.cpp101 bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
104 bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
118 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
122 unsigned Reg);
125 unsigned Reg);
173 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
219 "Reg should not have empty live interval.");
315 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist, argument
319 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
359 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, argument
401 isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives) argument
434 isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) argument
451 findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys) argument
479 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) argument
666 unsigned Reg = DstReg; local
745 rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi, unsigned Reg) argument
914 isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI) argument
937 rescheduleKillAboveMI(MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi, unsigned Reg) argument
1196 unsigned Reg = MRI->createVirtualRegister(RC); local
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H A DVirtRegMap.cpp122 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
123 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
124 OS << '[' << PrintReg(Reg, TRI) << " -> "
125 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
126 << MRI->getRegClass(Reg)->getName() << "\n";
131 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
132 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
133 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
134 << "] " << MRI->getRegClass(Reg)
416 unsigned Reg = *I; local
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp162 unsigned Reg = lookUpRegForValue(V); local
163 if (Reg != 0)
164 return Reg;
177 Reg = materializeRegForValue(V, VT);
181 return Reg;
188 unsigned Reg = 0; local
192 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
194 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
198 Reg =
202 Reg
271 UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) argument
587 unsigned Reg = getRegForValue(Val); local
876 unsigned Reg = getRegForValue(I->getOperand(0)); local
1192 unsigned Reg = getRegForValue(I->getOperand(0)); local
1663 unsigned Reg = getRegForValue(PHIOp); local
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H A DFunctionLoweringInfo.cpp285 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) { argument
286 if (!LiveOutRegInfo.inBounds(Reg))
289 LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
H A DInstrEmitter.cpp199 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); local
200 if (TargetRegisterInfo::isVirtualRegister(Reg))
201 return Reg;
248 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); local
249 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
250 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
252 VRBase = Reg;
823 unsigned Reg = II.getImplicitDefs()[i - NumDefs];
827 UsedRegs.push_back(Reg);
828 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMa
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H A DScheduleDAGFast.cpp388 void ScheduleDAGFast::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, argument
418 SDep FromDep(SU, SDep::Data, Reg);
434 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, argument
440 if (Reg == *ImpDef)
449 static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg, argument
455 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
503 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); local
504 if (TargetRegisterInfo::isPhysicalRegister(Reg))
505 CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
517 for (const uint16_t *Reg
573 unsigned Reg = LRegs[0]; local
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H A DScheduleDAGRRList.cpp1 //===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===//
237 void releaseInterferences(unsigned Reg = 0);
291 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); local
292 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
1137 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, argument
1173 SDep FromDep(SU, SDep::Data, Reg);
1192 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, argument
1198 if (Reg == *ImpDef)
1207 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg, argument
1212 for (MCRegAliasIterator AliasI(Reg, TR
1291 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); local
1330 releaseInterferences(unsigned Reg) argument
1397 unsigned Reg = LRegs[j]; local
1440 unsigned Reg = LRegs[0]; local
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H A DScheduleDAGSDNodes.cpp118 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); local
119 if (TargetRegisterInfo::isVirtualRegister(Reg))
126 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
127 PhysReg = Reg;
129 TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo));
641 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
642 if (TargetRegisterInfo::isVirtualRegister(Reg))
768 unsigned Reg = 0;
773 Reg = II->getReg();
777 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
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H A DSelectionDAGBuilder.cpp614 unsigned Reg, Type *Ty) {
622 Regs.push_back(Reg + i);
624 Reg += NumRegs;
841 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
845 assert(Reg < Regs.size() && "Mismatch in # registers expected");
846 unsigned TheReg = Regs[Reg++];
1315 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1316 CopyValueToVirtualRegister(V, Reg);
1726 assert(JT.Reg != -1U && "Should lower JT Header first!");
1729 JT.Reg, PT
613 RegsForValue(LLVMContext &Context, const TargetLowering &tli, unsigned Reg, Type *Ty) argument
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H A DSelectionDAGBuilder.h238 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
240 /// Reg - the virtual register containing the index of the jump table entry
242 unsigned Reg; member in struct:llvm::SelectionDAGBuilder::JumpTable
280 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
285 unsigned Reg; member in struct:llvm::SelectionDAGBuilder::BitTestBlock
588 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
683 unsigned Reg,
H A DSelectionDAGISel.cpp470 unsigned Reg = local
472 if (TargetRegisterInfo::isPhysicalRegister(Reg))
475 MachineInstr *Def = RegInfo->getVRegDef(Reg);
482 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
485 // If Reg is live-in then update debug info to track its copy in a vreg.
486 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
911 if (unsigned Reg = TLI->getExceptionPointerRegister())
912 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
915 if (unsigned Reg = TLI->getExceptionSelectorRegister())
916 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrR
1864 unsigned Reg = getTargetLowering()->getRegisterByName( local
1877 unsigned Reg = getTargetLowering()->getRegisterByName( local
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/external/llvm/lib/MC/MCAnalysis/
H A DMCModuleYAML.cpp67 bool matchRegister(StringRef Name, unsigned &Reg) { argument
71 Reg = It->getValue();
242 unsigned Reg; local
243 if (!IRI->matchRegister(Scalar.substr(1), Reg))
245 Val.MCOp = MCOperand::CreateReg(Reg);
/external/llvm/lib/MC/
H A DMCDwarf.cpp1108 unsigned Reg = Instr.getRegister(); local
1111 Streamer.AddComment(Twine("Reg ") + Twine(Reg));
1114 Streamer.EmitULEB128IntValue(Reg);
1143 Streamer.AddComment(Twine("Reg ") + Twine(Instr.getRegister()));
1161 Streamer.AddComment(Twine("Reg ") + Twine(Instr.getRegister()));
1172 unsigned Reg = Instr.getRegister(); local
1181 if (VerboseAsm) Streamer.AddComment(Twine("Reg ") + Twine(Reg));
1182 Streamer.EmitULEB128IntValue(Reg);
1210 unsigned Reg = Instr.getRegister(); local
1218 unsigned Reg = Instr.getRegister(); local
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H A DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument
20 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { argument
31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
/external/llvm/lib/MC/MCParser/
H A DCOFFAsmParser.cpp581 unsigned Reg; local
582 if (ParseSEHRegisterNumber(Reg))
589 getStreamer().EmitWinCFIPushReg(Reg);
594 unsigned Reg; local
596 if (ParseSEHRegisterNumber(Reg))
613 getStreamer().EmitWinCFISetFrame(Reg, Off);
635 unsigned Reg; local
637 if (ParseSEHRegisterNumber(Reg))
655 getStreamer().EmitWinCFISaveReg(Reg, Off);
662 unsigned Reg; local
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/external/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp491 for (auto Reg : Ord) {
492 if (!AvailableRegs[Reg])
494 if ((C == Color::Even && (Reg % 2) == 0) ||
495 (C == Color::Odd && (Reg % 2) == 1))
496 return Reg;
510 int Reg = scavengeRegister(G, C, MBB); local
511 if (Reg == -1) {
515 DEBUG(dbgs() << " - Scavenged register: " << TRI->getName(Reg) << "\n");
555 Substs[MO.getReg()] = Reg;
556 MO.setReg(Reg);
688 getColor(unsigned Reg) argument
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H A DAArch64AdvSIMDScalarPass.cpp100 static bool isGPR64(unsigned Reg, unsigned SubReg, argument
104 if (TargetRegisterInfo::isVirtualRegister(Reg))
105 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
106 return AArch64::GPR64RegClass.contains(Reg);
109 static bool isFPR64(unsigned Reg, unsigned SubReg, argument
111 if (TargetRegisterInfo::isVirtualRegister(Reg))
112 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
114 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
117 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
118 (AArch64::FPR128RegClass.contains(Reg)
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