Searched refs:CTLZ (Results 1 - 24 of 24) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h314 BSWAP, CTTZ, CTLZ, CTPOP, enumerator in enum:llvm::ISD::NodeType
/external/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp183 Function *CTLZ = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, local
255 Value *Tmp0 = Builder.CreateCall2(CTLZ, Divisor, True);
256 Value *Tmp1 = Builder.CreateCall2(CTLZ, Dividend, True);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp288 case ISD::CTLZ: return "ctlz";
H A DLegalizeVectorTypes.cpp71 case ISD::CTLZ:
586 case ISD::CTLZ:
1212 case ISD::CTLZ:
1619 case ISD::CTLZ:
H A DLegalizeDAG.cpp2774 // This trivially expands to CTLZ.
2775 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2776 case ISD::CTLZ: {
2810 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2812 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2815 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2961 case ISD::CTLZ:
4151 case ISD::CTLZ:
4166 } else if (Node->getOpcode() == ISD::CTLZ ||
H A DLegalizeVectorOps.cpp259 case ISD::CTLZ:
H A DLegalizeIntegerTypes.cpp62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
1137 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
H A DDAGCombiner.cpp1225 case ISD::CTLZ: return visitCTLZ(N);
4364 if (N1C && N0.getOpcode() == ISD::CTLZ &&
4381 // could be set on input to the CTLZ node. If this bit is set, the SRL
4382 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
4460 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
11338 TLI.isOperationLegal(ISD::CTLZ, XType))) {
11339 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0);
H A DTargetLowering.cpp1240 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
H A DSelectionDAG.cpp2145 case ISD::CTLZ:
2705 case ISD::CTLZ:
H A DSelectionDAGBuilder.cpp5195 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp123 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
124 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDILISelLowering.cpp158 setOperationAction(ISD::CTLZ, VT, Expand);
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILISelLowering.cpp158 setOperationAction(ISD::CTLZ, VT, Expand);
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1408 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1409 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp239 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
240 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
241 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp259 setOperationAction(ISD::CTLZ, Ty, Legal);
2026 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
H A DMipsISelLowering.cpp368 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
370 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
/external/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp260 setOperationAction(ISD::CTLZ, VT, Expand);
324 setOperationAction(ISD::CTLZ, VT, Expand);
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1473 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1528 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp208 // We have native support for a 64-bit CTLZ, via FLOGR.
209 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
210 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp497 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
506 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
850 setOperationAction(ISD::CTLZ, VT, Expand);
1448 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1449 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
16228 case ISD::CTLZ
[all...]
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp641 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
643 // These just redirect to CTTZ and CTLZ on ARM.
4097 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp464 setOperationAction(ISD::CTLZ, VT, Expand);
1755 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);

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