Searched refs:v4i32 (Results 1 - 25 of 36) sorted by relevance

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/external/clang/test/CodeGen/
H A Dmips-vector-arg.c9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
24 extern test_v4i32_2(v4i32, int, v4i32);
25 void test_v4i32(v4i32 a1, int a2, v4i32 a3) {
H A Dmips-inline-asm-modifiers.c8 typedef int v4i32 __attribute__((vector_size(16))); typedef
17 v4i32 v4i32_r;
H A Dmips-vector-return.c9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
28 v4i32 test_v4i32(int a) {
29 return (v4i32){0, a, 0, 0};
H A Dcompound-literal.c6 typedef int v4i32 __attribute((vector_size(16))); typedef
7 v4i32 *y = &(v4i32){1,2,3,4};
H A Dmips-varargs.c10 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
192 v4i32 v = va_arg(va, v4i32);
H A Dsystemz-abi-vector.c24 typedef __attribute__((vector_size(16))) int v4i32; typedef
69 v4i32 pass_v4i32(v4i32 arg) { return arg; }
H A Dx86_32-arguments-darwin.c224 typedef int v4i32 __attribute__((__vector_size__(16))); typedef
228 v4i32 f55(v4i32 arg) { return arg+arg; }
H A Dbuiltins-mips-msa.c7 typedef signed int v4i32 __attribute__ ((vector_size(16))); typedef
24 v4i32 v4i32_a = (v4i32) {0, 1, 2, 3};
25 v4i32 v4i32_b = (v4i32) {1, 2, 3, 4};
26 v4i32 v4i32_r;
/external/llvm/lib/Target/R600/
H A DSITypeRewriter.cpp38 Type *v4i32; member in class:__anon10864::SITypeRewriter
59 v4i32 = VectorType::get(Type::getInt32Ty(M.getContext()), 4);
87 PointerType::get(v4i32,PtrTy->getPointerAddressSpace()));
111 Args.push_back(Builder.CreateBitCast(Arg, v4i32));
112 Types.push_back(v4i32);
114 Name = Name + ".v4i32";
147 if (I.getDestTy() != v4i32) {
152 if (Op->getSrcTy() == v4i32) {
H A DR600ISelLowering.cpp38 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
67 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
92 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
121 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
142 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
147 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
152 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
157 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1353 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Sr
[all...]
H A DSIISelLowering.cpp54 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
83 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
91 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
347 return MVT::v4i32;
1290 // prevent a mess from expanding to v4i32 and repacking.
2019 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
2031 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
2068 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp139 { ISD::SHL, MVT::v4i32, 1 },
140 { ISD::SRL, MVT::v4i32, 1 },
141 { ISD::SRA, MVT::v4i32, 1 },
197 { ISD::SHL, MVT::v4i32, 1 }, // pslld
202 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
207 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
211 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
212 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence
218 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
230 (VT == MVT::v4i32
[all...]
H A DX86ISelLowering.cpp793 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
803 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
810 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
812 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
813 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
832 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
837 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
844 setOperationAction(ISD::CTPOP, MVT::v4i32, Custo
[all...]
/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp81 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
82 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
85 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
86 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
105 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
106 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
129 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
130 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
351 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
374 {ISD::VECTOR_SHUFFLE, MVT::v4i32,
[all...]
H A DARMISelLowering.cpp159 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
440 addQRTypeForNEON(MVT::v4i32);
519 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
544 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
573 // It is legal to extload from v4i8 to v4i16 or v4i32.
990 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
3793 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3845 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
4060 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
4216 /// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vecto
[all...]
/external/llvm/include/llvm/CodeGen/
H A DMachineValueType.h81 v4i32 = 34, // 4 x i32 enumerator in enum:llvm::MVT::SimpleValueType
226 SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
305 case v4i32:
354 case v4i32:
428 case v4i32:
554 if (NumElements == 4) return MVT::v4i32;
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp472 case MVT::v4i32:
499 case MVT::v4i32:
510 case MVT::v4i32:
2268 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2286 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2304 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2322 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2340 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2358 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2376 else if (VT == MVT::v4i32 || V
[all...]
H A DAArch64TargetTransformInfo.cpp193 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
196 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
224 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
227 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
H A DAArch64ISelLowering.cpp116 addQRTypeForNEON(MVT::v4i32);
572 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
573 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
574 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
580 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
583 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
697 addTypeForNEON(VT, MVT::v4i32);
3385 VecVT = MVT::v4i32;
5381 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5390 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32
[all...]
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86InstComments.cpp50 DstVT = MVT::v4i32;
75 DstVT = MVT::v4i32;
99 SrcVT = MVT::v4i32;
104 SrcVT = MVT::v4i32;
208 DecodeBLENDMask(MVT::v4i32,
381 DecodePSHUFMask(MVT::v4i32,
486 DecodeUNPCKHMask(MVT::v4i32, ShuffleMask);
575 DecodeUNPCKLMask(MVT::v4i32, ShuffleMask);
878 DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask);
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600GenRegisterInfo.pl97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
H A DAMDILISelLowering.cpp62 (int)MVT::v4i32,
90 (int)MVT::v4i32,
504 INTTY = MVT::v4i32;
651 INTTY = MVT::v4i32;
669 INTTY = MVT::v4i32;
/external/llvm/lib/IR/
H A DValueTypes.cpp152 case MVT::v4i32: return "v4i32";
220 case MVT::v4i32: return VectorType::get(Type::getInt32Ty(Context), 4);
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp422 // We promote all non-typed operations to v4i32.
424 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
426 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
428 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
430 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
432 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
434 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
490 setOperationAction(ISD::AND , MVT::v4i32, Legal);
491 setOperationAction(ISD::OR , MVT::v4i32, Legal);
492 setOperationAction(ISD::XOR , MVT::v4i32, Lega
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp212 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
253 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))

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