/drivers/tty/serial/ |
H A D | bfin_sport_uart.h | 34 #define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1)) 35 #define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2)) 36 #define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV)) 37 #define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV)) 38 #define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX)) 39 #define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX)) 51 __ret = bfin_read32((sport)->port.membase + OFFSET_RX); \ 56 #define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1)) 57 #define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2)) 58 #define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase [all...] |
H A D | netx-serial.c | 121 val = readl(port->membase + UART_CR); 122 writel(val & ~CR_TIE, port->membase + UART_CR); 128 val = readl(port->membase + UART_CR); 129 writel(val & ~CR_RIE, port->membase + UART_CR); 135 val = readl(port->membase + UART_CR); 136 writel(val | CR_MSIE, port->membase + UART_CR); 144 writel(port->x_char, port->membase + UART_DR); 158 writel(xmit->buf[xmit->tail], port->membase + UART_DR); 164 } while (!(readl(port->membase + UART_FR) & FR_TXFF)); 173 readl(port->membase [all...] |
H A D | timbuart.c | 54 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; 55 iowrite32(ier, port->membase + TIMBUART_IER); 61 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; 62 iowrite32(ier, port->membase + TIMBUART_IER); 76 u32 isr = ioread32(port->membase + TIMBUART_ISR); 84 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | 87 iowrite8(ctl, port->membase + TIMBUART_CTRL); 88 iowrite32(TXBF, port->membase + TIMBUART_ISR); 96 while (ioread32(port->membase + TIMBUART_ISR) & RXDP) { 97 u8 ch = ioread8(port->membase [all...] |
H A D | mcf.c | 67 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ? 78 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ? 96 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); 98 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0); 109 writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR); 111 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); 114 writeb(pp->imr, port->membase + MCFUART_UIMR); 124 writeb(pp->imr, port->membase + MCFUART_UIMR); 134 writeb(pp->imr, port->membase + MCFUART_UIMR); 145 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase [all...] |
H A D | imx.c | 310 ucr->ucr1 = readl(port->membase + UCR1); 311 ucr->ucr2 = readl(port->membase + UCR2); 312 ucr->ucr3 = readl(port->membase + UCR3); 319 writel(ucr->ucr1, port->membase + UCR1); 320 writel(ucr->ucr2, port->membase + UCR2); 321 writel(ucr->ucr3, port->membase + UCR3); 382 !(readl(sport->port.membase + USR2) & USR2_TXDC)) { 396 if (readl(sport->port.membase + USR2) & USR2_TXDC) { 397 temp = readl(sport->port.membase + UCR1); 399 writel(temp, sport->port.membase [all...] |
H A D | lpc32xx_hs.c | 111 port->membase))) == 0) 125 port->membase))) < 32) 136 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); 176 if (!port->membase) 253 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && 255 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 264 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 272 LPC32XX_HSUART_IIR(port->membase)); 280 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 294 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); [all...] |
H A D | lantiq.c | 154 ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); 163 fifocnt = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; 166 ch = ltq_r8(port->membase + LTQ_ASC_RBUF); 167 rsr = (ltq_r32(port->membase + LTQ_ASC_STATE) 180 port->membase + LTQ_ASC_WHBSTATE); 184 port->membase + LTQ_ASC_WHBSTATE); 189 port->membase + LTQ_ASC_WHBSTATE); 227 while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) & 230 ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF); 240 port->membase [all...] |
H A D | meson_uart.c | 102 val = readl(port->membase + AML_UART_STATUS); 110 val = readl(port->membase + AML_UART_CONTROL); 112 writel(val, port->membase + AML_UART_CONTROL); 119 val = readl(port->membase + AML_UART_CONTROL); 121 writel(val, port->membase + AML_UART_CONTROL); 133 val = readl(port->membase + AML_UART_CONTROL); 136 writel(val, port->membase + AML_UART_CONTROL); 151 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { 153 writel(port->x_char, port->membase + AML_UART_WFIFO); 163 writel(ch, port->membase [all...] |
H A D | mxs-auart.c | 284 while (!(readl(s->port.membase + AUART_STAT) & 289 s->port.membase + AUART_DATA); 296 s->port.membase + AUART_DATA); 306 s->port.membase + AUART_INTR_CLR); 309 s->port.membase + AUART_INTR_SET); 321 c = readl(s->port.membase + AUART_DATA); 322 stat = readl(s->port.membase + AUART_STAT); 357 writel(stat, s->port.membase + AUART_STAT); 365 stat = readl(s->port.membase + AUART_STAT); 371 writel(stat, s->port.membase [all...] |
H A D | fsl_lpuart.c | 288 temp = readb(port->membase + UARTCR2); 290 writeb(temp, port->membase + UARTCR2); 297 temp = lpuart32_read(port->membase + UARTCTRL); 299 lpuart32_write(temp, port->membase + UARTCTRL); 306 temp = readb(port->membase + UARTCR2); 307 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 314 temp = lpuart32_read(port->membase + UARTCTRL); 315 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL); 352 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) { 353 writeb(xmit->buf[xmit->tail], sport->port.membase [all...] |
H A D | amba-pl010.c | 81 cr = readb(uap->port.membase + UART010_CR); 83 writel(cr, uap->port.membase + UART010_CR); 91 cr = readb(uap->port.membase + UART010_CR); 93 writel(cr, uap->port.membase + UART010_CR); 101 cr = readb(uap->port.membase + UART010_CR); 103 writel(cr, uap->port.membase + UART010_CR); 111 cr = readb(uap->port.membase + UART010_CR); 113 writel(cr, uap->port.membase + UART010_CR); 120 status = readb(uap->port.membase + UART01x_FR); 122 ch = readb(uap->port.membase [all...] |
H A D | altera_jtaguart.c | 68 return (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) & 87 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); 96 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); 105 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); 127 while ((status = readl(port->membase + ALTERA_JTAGUART_DATA_REG)) & 151 writel(port->x_char, port->membase + ALTERA_JTAGUART_DATA_REG); 159 count = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) & 168 port->membase + ALTERA_JTAGUART_DATA_REG); 179 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); 190 isr = (readl(port->membase [all...] |
H A D | amba-pl011.c | 182 status = readw(uap->port.membase + UART01x_FR); 187 ch = readw(uap->port.membase + UART01x_DR) | 432 writew(uap->dmacr, uap->port.membase + UART011_DMACR); 456 writew(uap->im, uap->port.membase + UART011_IMSC); 543 writew(uap->dmacr, uap->port.membase + UART011_DMACR); 579 writew(uap->dmacr, uap->port.membase + UART011_DMACR); 581 writew(uap->im, uap->port.membase + UART011_IMSC); 591 writew(uap->im, uap->port.membase + UART011_IMSC); 605 writew(uap->dmacr, uap->port.membase + UART011_DMACR); 636 writew(uap->im, uap->port.membase [all...] |
/drivers/net/phy/ |
H A D | mdio-sun4i.c | 35 void __iomem *membase; member in struct:sun4i_mdio_data 46 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); 48 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); 52 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) { 59 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); 61 value = readl(data->membase + EMAC_MAC_MRDD_REG); 73 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); 75 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); 79 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) { 86 writel(0x0, data->membase [all...] |
/drivers/isdn/hisax/ |
H A D | telespci.c | 183 return (readisac(cs->hw.teles0.membase, offset)); 189 writeisac(cs->hw.teles0.membase, offset, value); 195 read_fifo_isac(cs->hw.teles0.membase, data, size); 201 write_fifo_isac(cs->hw.teles0.membase, data, size); 207 return (readhscx(cs->hw.teles0.membase, hscx, offset)); 213 writehscx(cs->hw.teles0.membase, hscx, offset, value); 220 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg) 221 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data) 222 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt) 223 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, n [all...] |
H A D | teles0.c | 100 return (readisac(cs->hw.teles0.membase, offset)); 106 writeisac(cs->hw.teles0.membase, offset, value); 112 read_fifo_isac(cs->hw.teles0.membase, data, size); 118 write_fifo_isac(cs->hw.teles0.membase, data, size); 124 return (readhscx(cs->hw.teles0.membase, hscx, offset)); 130 writehscx(cs->hw.teles0.membase, hscx, offset, value); 137 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg) 138 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data) 139 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt) 140 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, n [all...] |
/drivers/net/ethernet/allwinner/ |
H A D | sun4i-emac.c | 71 void __iomem *membase; member in struct:emac_board_info 94 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); 98 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); 107 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); 111 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); 192 writel(0, db->membase + EMAC_CTL_REG); 194 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); 266 reg_val = readl(db->membase + EMAC_TX_MODE_REG); 269 db->membase + EMAC_TX_MODE_REG); 273 reg_val = readl(db->membase [all...] |
/drivers/atm/ |
H A D | idt77252.h | 352 void __iomem *membase; /* SAR's memory base address */ member in struct:idt77252_dev 438 #define SAR_REG_DR0 (card->membase + 0x00) 439 #define SAR_REG_DR1 (card->membase + 0x04) 440 #define SAR_REG_DR2 (card->membase + 0x08) 441 #define SAR_REG_DR3 (card->membase + 0x0C) 442 #define SAR_REG_CMD (card->membase + 0x10) 443 #define SAR_REG_CFG (card->membase + 0x14) 444 #define SAR_REG_STAT (card->membase + 0x18) 445 #define SAR_REG_RSQB (card->membase + 0x1C) 446 #define SAR_REG_RSQT (card->membase [all...] |
/drivers/reset/ |
H A D | reset-socfpga.c | 31 void __iomem *membase; member in struct:socfpga_reset_data 48 reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS)); 49 writel(reg | BIT(offset), data->membase + OFFSET_MODRST + 70 reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS)); 71 writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST + 104 data->membase = devm_ioremap_resource(&pdev->dev, res); 105 if (IS_ERR(data->membase)) 106 return PTR_ERR(data->membase);
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H A D | reset-sunxi.c | 27 void __iomem *membase; member in struct:sunxi_reset_data 44 reg = readl(data->membase + (bank * 4)); 45 writel(reg & ~BIT(offset), data->membase + (bank * 4)); 65 reg = readl(data->membase + (bank * 4)); 66 writel(reg | BIT(offset), data->membase + (bank * 4)); 99 data->membase = ioremap(res.start, size); 100 if (!data->membase) { 156 data->membase = devm_ioremap_resource(&pdev->dev, res); 157 if (IS_ERR(data->membase)) 158 return PTR_ERR(data->membase); [all...] |
/drivers/gpio/ |
H A D | gpio-timberdale.c | 46 void __iomem *membase; member in struct:timbgpio 60 reg = ioread32(tgpio->membase + offset); 67 iowrite32(reg, tgpio->membase + offset); 83 value = ioread32(tgpio->membase + TGPIOVAL); 120 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); 132 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); 148 ver = ioread32(tgpio->membase + TGPIO_VER); 152 lvr = ioread32(tgpio->membase + TGPIO_LVR); 153 flr = ioread32(tgpio->membase + TGPIO_FLR); 155 bflr = ioread32(tgpio->membase [all...] |
H A D | gpio-mvebu.c | 81 void __iomem *membase; member in struct:mvebu_gpio_chip 94 return mvchip->membase + GPIO_OUT_OFF; 99 return mvchip->membase + GPIO_BLINK_EN_OFF; 104 return mvchip->membase + GPIO_IO_CONF_OFF; 109 return mvchip->membase + GPIO_IN_POL_OFF; 114 return mvchip->membase + GPIO_DATA_IN_OFF; 124 return mvchip->membase + GPIO_EDGE_CAUSE_OFF; 139 return mvchip->membase + GPIO_EDGE_MASK_OFF; 142 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); 157 return mvchip->membase [all...] |
/drivers/input/keyboard/ |
H A D | locomokbd.c | 87 static inline void locomokbd_charge_all(unsigned long membase) argument 89 locomo_writel(0x00FF, membase + LOCOMO_KSC); 92 static inline void locomokbd_activate_all(unsigned long membase) argument 96 locomo_writel(0, membase + LOCOMO_KSC); 97 r = locomo_readl(membase + LOCOMO_KIC); 99 locomo_writel(r, membase + LOCOMO_KIC); 102 static inline void locomokbd_activate_col(unsigned long membase, int col) argument 109 locomo_writel(nbset, membase + LOCOMO_KSC); 112 static inline void locomokbd_reset_col(unsigned long membase, int col) argument 117 locomo_writel(nbset, membase 132 unsigned long membase = locomokbd->base; local [all...] |
/drivers/net/ethernet/sfc/ |
H A D | io.h | 85 __raw_writeq((__force u64)value, efx->membase + reg); 89 return (__force __le64)__raw_readq(efx->membase + reg); 96 __raw_writel((__force u32)value, efx->membase + reg); 100 return (__force __le32)__raw_readl(efx->membase + reg); 128 static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase, argument 140 __raw_writeq((__force u64)value->u64[0], membase + addr); 142 __raw_writel((__force u32)value->u32[0], membase + addr); 143 __raw_writel((__force u32)value->u32[1], membase + addr + 4); 180 static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase, argument 188 value->u64[0] = (__force __le64)__raw_readq(membase [all...] |
/drivers/tty/serial/8250/ |
H A D | 8250_early.c | 45 return readb(port->membase + offset); 47 return readl(port->membase + (offset << 2)); 59 writeb(value, port->membase + offset); 62 writel(value, port->membase + (offset << 2)); 144 if (!(device->port.membase || device->port.iobase)) 179 if (!port || (!port->membase && !port->iobase))
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