/external/llvm/lib/Target/ARM/ |
H A D | Thumb1InstrInfo.cpp | 43 unsigned DestReg, unsigned SrcReg, 45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) 47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && 81 unsigned DestReg, int FI, 85 (TargetRegisterInfo::isPhysicalRegister(DestReg) && 86 isARMLowRegister(DestReg))) && "Unknown regclass!"); 89 (TargetRegisterInfo::isPhysicalRegister(DestReg) && 90 isARMLowRegister(DestReg))) { 101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) 41 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 80 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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H A D | Thumb2RegisterInfo.cpp | 38 unsigned DestReg, unsigned SubIdx, 49 .addReg(DestReg, getDefRegState(true), SubIdx) 35 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | Thumb2InstrInfo.cpp | 114 unsigned DestReg, unsigned SrcReg, 117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) 118 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); 120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) 153 unsigned DestReg, int FI, 169 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) 174 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI); 179 unsigned DestReg, unsigned BaseReg, int NumBytes, 187 if (DestReg != ARM::SP && DestReg ! 112 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 152 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 177 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument [all...] |
H A D | Thumb1RegisterInfo.cpp | 68 unsigned DestReg, unsigned SubIdx, 79 .addReg(DestReg, getDefRegState(true), SubIdx) 93 unsigned DestReg, unsigned BaseReg, 99 bool isHigh = !isARMLowRegister(DestReg) || 110 unsigned LdReg = DestReg; 111 if (DestReg == ARM::SP) { 131 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); 134 if (DestReg == ARM::SP || isSub) 170 unsigned DestReg, unsigned BaseReg, 186 if (DestReg 65 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument 90 emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags = MachineInstr::NoFlags) argument 167 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags) argument 342 emitThumbConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Imm, const TargetInstrInfo &TII, const Thumb1RegisterInfo& MRI, DebugLoc dl) argument [all...] |
H A D | ARMBaseRegisterInfo.cpp | 708 unsigned DestReg, unsigned SubIdx, int Val, 718 .addReg(DestReg, getDefRegState(true), SubIdx) 705 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonSplitTFRCondSets.cpp | 89 int DestReg = MI->getOperand(0).getReg(); local 105 if (DestReg != SrcReg1) { 107 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 109 if (DestReg != SrcReg2) { 111 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); 119 int DestReg = MI->getOperand(0).getReg(); local 124 if (DestReg != SrcReg1) { 126 TII->get(Hexagon::TFR_cPt), DestReg). 131 TII->get(Hexagon::TFRI_cNotPt), DestReg). 136 TII->get(Hexagon::TFRI_cNotPt_f), DestReg) 147 int DestReg = MI->getOperand(0).getReg(); local 175 int DestReg = MI->getOperand(0).getReg(); local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | Mips16InstrInfo.cpp | 59 unsigned DestReg, unsigned SrcReg, 63 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg. 72 if (DestReg) 73 MIB.addReg(DestReg, RegState::Define); 92 unsigned DestReg, int FI, 57 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 91 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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H A D | MipsSEInstrInfo.cpp | 87 unsigned DestReg, unsigned SrcReg, 91 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg. 104 if (Mips::CCRRegClass.contains(DestReg)) 106 else if (Mips::FGR32RegClass.contains(DestReg)) 108 else if (DestReg == Mips::HI) 109 Opc = Mips::MTHI, DestReg = 0; 110 else if (DestReg == Mips::LO) 111 Opc = Mips::MTLO, DestReg = 0; 113 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) 115 else if (Mips::AFGR64RegClass.contains(DestReg, SrcRe 85 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 182 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
H A D | MipsISelDAGToDAG.cpp | 545 unsigned RdhwrOpc, SrcReg, DestReg; local 550 DestReg = Mips::V1; 554 DestReg = Mips::V1_64; 561 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg, 563 SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeInstrInfo.cpp | 86 unsigned DestReg, unsigned SrcReg, 88 llvm::BuildMI(MBB, I, DL, get(MBlaze::ADDK), DestReg) 104 unsigned DestReg, int FI, 108 BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg) 84 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 103 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 64 unsigned DestReg, int FrameIdx, 80 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); 83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); 90 unsigned DestReg, unsigned SrcReg, 93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) 95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) 100 BuildMI(MBB, I, DL, get(Opc), DestReg) 62 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 88 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 38 unsigned DestReg, unsigned SrcReg, 40 if (NVPTX::Int32RegsRegClass.contains(DestReg) && 42 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg) 44 else if (NVPTX::Int8RegsRegClass.contains(DestReg) && 46 BuildMI(MBB, I, DL, get(NVPTX::IMOV8rr), DestReg) 48 else if (NVPTX::Int1RegsRegClass.contains(DestReg) && 50 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg) 52 else if (NVPTX::Float32RegsRegClass.contains(DestReg) && 54 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg) 56 else if (NVPTX::Int16RegsRegClass.contains(DestReg) 36 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | LiveRangeEdit.cpp | 137 unsigned DestReg, 142 TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri); 135 rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &tri, bool Late) argument
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H A D | PHIElimination.cpp | 209 unsigned DestReg = MPhi->getOperand(0).getReg(); local 226 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); 238 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); 242 TII->get(TargetOpcode::COPY), DestReg) 281 LV->addVirtualRegisterDead(DestReg, PHICopy); 282 LV->removeVirtualRegisterDead(DestReg, MPhi);
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H A D | StrongPHIElimination.cpp | 243 unsigned DestReg = BBI->getOperand(0).getReg(); local 244 addReg(DestReg); 251 unionRegs(DestReg, SrcReg); 287 unsigned DestReg = BBI->getOperand(0).getReg(); local 288 addReg(DestReg); 293 unionRegs(DestReg, SrcReg); 317 unsigned DestReg = PHI->getOperand(0).getReg(); local 318 if (!InsertedDestCopies.count(DestReg)) 319 MergeLIsAndRename(DestReg, NewReg); 340 unsigned DestReg local 460 unsigned DestReg = PHI->getOperand(0).getReg(); local 541 unsigned DestReg = MO.getReg(); local 738 unsigned DestReg = PHI->getOperand(0).getReg(); local [all...] |
H A D | TargetInstrInfoImpl.cpp | 224 unsigned DestReg, 229 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); 222 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 281 unsigned DestReg = ValueMap[PN]; local 282 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 284 LiveOutRegInfo.grow(DestReg); 285 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
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H A D | InstrEmitter.cpp | 116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); local 117 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 118 VRBase = DestReg; 120 } else if (DestReg != SrcReg) 468 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 469 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 470 VRBase = DestReg; 856 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 857 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 861 DestReg) [all...] |
/external/llvm/lib/Target/CellSPU/ |
H A D | SPUInstrInfo.cpp | 126 unsigned DestReg, unsigned SrcReg, 134 BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg) 174 unsigned DestReg, int FrameIdx, 200 addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx); 124 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 172 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.cpp | 282 unsigned DestReg, unsigned SrcReg, 284 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) 285 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) 287 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) 288 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) 290 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) 291 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg) 321 unsigned DestReg, int FI, 328 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); 330 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg) 280 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 320 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 336 unsigned DestReg, unsigned SrcReg, 338 bool GRDest = XCore::GRRegsRegClass.contains(DestReg); 342 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) 349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); 353 if (DestReg == XCore::SP && GRSrc) { 378 unsigned DestReg, int FrameIndex, 384 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) 334 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 376 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 207 unsigned DestReg) { 209 .addReg(DestReg, RegState::Define); 220 unsigned DestReg) { 223 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define); 230 unsigned DestReg) { 233 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define); 240 unsigned DestReg) { 243 return BuildMI(BB, MII, DL, MCID, DestReg); 247 return BuildMI(BB, MII, DL, MCID, DestReg); 302 unsigned DestReg) { 204 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument 216 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument 226 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument 236 BuildMI(MachineBasicBlock &BB, MachineInstr *I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument 299 BuildMI(MachineBasicBlock *BB, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 415 unsigned DestReg, unsigned SrcReg, 418 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) 420 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) 422 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) 424 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) 426 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 428 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 435 BuildMI(MBB, I, DL, MCID, DestReg) 438 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); 614 unsigned DestReg, in 413 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 613 LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 722 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
H A D | PPCRegisterInfo.cpp | 442 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 456 unsigned DestReg = MI.getOperand(0).getReg(); local 457 assert(MI.definesRegister(DestReg) && 465 if (DestReg != PPC::CR0) { 466 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 473 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg)
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/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 183 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 187 unsigned DestReg, unsigned SubIdx, 471 unsigned DestReg, unsigned SrcReg, 496 unsigned DestReg, int FrameIndex, 994 unsigned DestReg, unsigned SubReg, 469 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 494 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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