Searched defs:BasePtr (Results 1 - 23 of 23) sorted by relevance

/external/llvm/lib/Target/X86/
H A DX86RegisterInfo.h52 /// BasePtr - X86 physical register used as a base ptr in complex stack
55 unsigned BasePtr; member in class:llvm::final
126 unsigned getBaseRegister() const { return BasePtr; }
H A DX86RegisterInfo.cpp81 BasePtr = Is64Bit ? X86::RBX : X86::ESI;
437 return MRI->canReserveReg(BasePtr);
478 unsigned BasePtr; local
483 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
485 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
487 BasePtr = StackPtr;
489 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
493 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
507 assert(BasePtr == FramePtr && "Expected the FP as base register");
/external/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h90 /// BasePtr - ARM physical register used as a base ptr in complex stack
93 unsigned BasePtr; member in class:llvm::ARMBaseRegisterInfo
162 unsigned getBaseRegister() const { return BasePtr; }
H A DThumb1FrameLowering.cpp105 unsigned BasePtr = RegInfo->getBaseRegister(); local
289 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
H A DARMISelLowering.cpp8418 SDValue BasePtr = LD->getBasePtr(); local
8419 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8424 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8533 SDValue BasePtr = St->getBasePtr(); local
8541 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
8544 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
8561 SDValue BasePtr = St->getBasePtr(); local
8564 BasePtr, S
[all...]
/external/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp116 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW); local
137 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
154 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
/external/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp71 unsigned BasePtr = getFrameRegister(MF); local
77 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
87 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
109 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
117 .addReg(BasePtr).addImm(HighOffset).addReg(0);
123 .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIISelLowering.cpp348 ConstantSDNode *BasePtr = dyn_cast<ConstantSDNode>(Ptr->getBasePtr()); local
349 assert(BasePtr);
364 uint64_t Index = BasePtr->getZExtValue();
/external/chromium_org/third_party/webrtc/voice_engine/test/auto_test/
H A Dvoe_standard_test.h138 VoEBase* BasePtr() const { function in class:voetest::VoETestManager
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIISelLowering.cpp348 ConstantSDNode *BasePtr = dyn_cast<ConstantSDNode>(Ptr->getBasePtr()); local
349 assert(BasePtr);
364 uint64_t Index = BasePtr->getZExtValue();
/external/clang/lib/AST/
H A DCXXInheritance.cpp105 const void *BasePtr = static_cast<const void*>(Base->getCanonicalDecl()); local
107 const_cast<void *>(BasePtr),
/external/llvm/lib/CodeGen/
H A DShadowStackGC.cpp68 IRBuilder<> &B, Value *BasePtr,
71 IRBuilder<> &B, Value *BasePtr,
350 ShadowStackGC::CreateGEP(LLVMContext &Context, IRBuilder<> &B, Value *BasePtr, argument
355 Value* Val = B.CreateGEP(BasePtr, Indices, Name);
363 ShadowStackGC::CreateGEP(LLVMContext &Context, IRBuilder<> &B, Value *BasePtr, argument
367 Value *Val = B.CreateGEP(BasePtr, Indices, Name);
/external/llvm/lib/Transforms/Scalar/
H A DLoopIdiomRecognize.cpp991 Value *BasePtr = local
995 if (mayLoopAccessLocation(BasePtr, AliasAnalysis::ModRef,
1000 deleteIfDeadInstruction(BasePtr, *SE, TLI);
1023 NewCall = Builder.CreateMemSet(BasePtr,
1047 NewCall = Builder.CreateCall3(MSP, BasePtr, PatternPtr, NumBytes);
H A DSROA.cpp1261 /// This will return the BasePtr if that is valid, or build a new GEP
1263 static Value *buildGEP(IRBuilderTy &IRB, Value *BasePtr, argument
1266 return BasePtr;
1271 return BasePtr;
1273 return IRB.CreateInBoundsGEP(BasePtr, Indices, NamePrefix + "sroa_idx");
1276 /// \brief Get a natural GEP off of the BasePtr walking through Ty toward
1286 Value *BasePtr, Type *Ty, Type *TargetTy,
1290 return buildGEP(IRB, BasePtr, Indices, NamePrefix);
1293 unsigned PtrSize = DL.getPointerTypeSizeInBits(BasePtr->getType());
1322 return buildGEP(IRB, BasePtr, Indice
1285 getNaturalGEPWithType(IRBuilderTy &IRB, const DataLayout &DL, Value *BasePtr, Type *Ty, Type *TargetTy, SmallVectorImpl<Value *> &Indices, Twine NamePrefix) argument
[all...]
/external/llvm/lib/Bitcode/Reader/
H A DBitcodeReader.cpp2435 Value *BasePtr; local
2436 if (getValueTypePair(Record, OpNum, NextValueNo, BasePtr))
2447 I = GetElementPtrInst::Create(BasePtr, GEPIdx);
/external/llvm/lib/Target/R600/
H A DSIISelLowering.cpp294 SDValue BasePtr = DAG.getCopyFromReg(Chain, DL, local
296 SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
H A DAMDGPUISelLowering.cpp1154 SDValue BasePtr = Load->getBasePtr(); local
1158 BasePtr, MVT::i8, MMO);
1246 SDValue BasePtr = Store->getBasePtr(); local
1247 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1252 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp439 SDValue BasePtr = LD->getBasePtr(); local
445 if (DAG.isBaseWithConstantOffset(BasePtr) &&
446 isWordAligned(BasePtr->getOperand(0), DAG)) {
447 SDValue NewBasePtr = BasePtr->getOperand(0);
448 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue();
452 if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) &&
455 BasePtr->getValueType(0));
463 BasePtr, LD->getPointerInfo(), MVT::i16,
465 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
481 // Lower to a call to __misaligned_load(BasePtr)
517 SDValue BasePtr = ST->getBasePtr(); local
[all...]
/external/clang/lib/CodeGen/
H A DCGClass.cpp617 llvm::Type *BasePtr = ConvertType(BaseElementTy); local
618 BasePtr = llvm::PointerType::getUnqual(BasePtr);
620 BasePtr);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp2735 SDValue BasePtr = LD->getBasePtr(); local
2749 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
2785 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2786 DAG.getConstant(Increment, BasePtr.getValueType()));
2793 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2809 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2888 SDValue BasePtr = LD->getBasePtr(); local
2902 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
2933 SDValue BasePtr = ST->getBasePtr(); local
3002 SDValue BasePtr = ST->getBasePtr(); local
[all...]
H A DDAGCombiner.cpp7620 SDValue BasePtr;
7623 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
7630 if (isa<ConstantSDNode>(BasePtr)) {
7631 std::swap(BasePtr, Offset);
7650 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
7656 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
7665 for (SDNode *Use : BasePtr.getNode()->uses()) {
7678 if (Op1.getNode() == BasePtr
7848 SDValue BasePtr; local
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp7275 SDValue BasePtr = St->getBasePtr(); local
7277 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7282 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7348 SDValue BasePtr = S->getBasePtr(); local
7350 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7352 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4937 SDValue BasePtr = LD->getBasePtr(); local
4941 BasePtr, MVT::i8, MMO);
4958 SDValue BasePtr = ST->getBasePtr(); local
4963 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
8261 SDNode *BasePtr = Add->getOperand(0).getNode(); local
8262 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8263 UE = BasePtr->use_end(); UI != UE; ++UI) {

Completed in 2549 milliseconds