Searched defs:ShiftAmt (Results 1 - 20 of 20) sorted by relevance

/external/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp75 const unsigned ShiftAmt = ToIdx * 16; local
78 const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt;
80 Imm &= ~(0xFFFFLL << ShiftAmt);
92 const unsigned ShiftAmt = ChunkIdx * 16;
112 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
173 unsigned ShiftAmt = 0;
176 for (; ShiftAmt < 64; ShiftAmt += 16) {
177 Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
190 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
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H A DAArch64ISelDAGToDAG.cpp239 unsigned ShiftAmt; local
242 ShiftAmt = 0;
244 ShiftAmt = 12;
249 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
1646 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); local
1647 Mask = Mask.shl(ShiftAmt);
1649 Mask = Mask.lshr(ShiftAmt);
1654 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); local
1655 Mask = Mask.lshr(ShiftAmt);
1657 Mask = Mask.shl(ShiftAmt);
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/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp609 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); local
610 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
615 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
617 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
623 KnownZero <<= ShiftAmt; local
624 KnownOne <<= ShiftAmt; local
626 if (ShiftAmt)
627 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
633 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); local
636 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
674 uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1); local
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H A DInstCombineCasts.cpp572 uint32_t ShiftAmt = KnownZeroMask.logBase2(); local
574 if (ShiftAmt) {
577 In = Builder->CreateLShr(In, ConstantInt::get(In->getType(),ShiftAmt),
712 uint64_t ShiftAmt = Amt->getZExtValue();
713 BitsToClear = ShiftAmt < BitsToClear ? BitsToClear - ShiftAmt : 0;
941 unsigned ShiftAmt = KnownZeroMask.countTrailingZeros(); local
943 if (ShiftAmt)
945 ConstantInt::get(In->getType(), ShiftAmt));
955 unsigned ShiftAmt local
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/external/llvm/lib/Analysis/
H A DConstantFolding.cpp176 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1); local
187 ConstantInt::get(Src->getType(), ShiftAmt));
188 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize;
208 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1); local
213 ConstantInt::get(Src->getType(), ShiftAmt));
214 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize;
H A DValueTracking.cpp478 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); local
480 KnownZero <<= ShiftAmt; local
481 KnownOne <<= ShiftAmt; local
482 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt); // low bits known 0
490 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); local
494 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
495 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt);
497 KnownZero |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
505 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); local
509 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp3338 uint64_t ShiftAmt = ShiftCnst->getZExtValue(); local
3361 NumBits = CountTrailingOnes_64(MaskVal) - ShiftAmt;
3368 NumBits = NumZeros + NumOnes - ShiftAmt;
3374 if (ShiftAmt < NumZeros) {
3381 Start = CurDAG->getTargetConstant(ShiftAmt, MVT::i32);
H A DNVPTXISelLowering.cpp2960 APInt ShiftAmt = ShlRHS->getAPIntValue(); local
2962 if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
2963 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
/external/llvm/lib/Target/R600/
H A DSIISelLowering.cpp972 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, local
977 MaskedValue, ShiftAmt);
979 DAG.getConstant(32, MVT::i32), ShiftAmt);
H A DAMDGPUISelLowering.cpp1197 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, local
1200 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1255 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, local
1264 MaskedValue, ShiftAmt);
1267 ShiftAmt);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp806 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy); local
808 Op.getValueType(), InOp, ShiftAmt));
2853 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits(); local
2854 SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT));
H A DDAGCombiner.cpp4186 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); local
4192 if ((ShiftAmt > 0) &&
4197 SDValue Amt = DAG.getConstant(ShiftAmt,
4344 uint64_t ShiftAmt = N1C->getZExtValue(); local
4347 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
4349 APInt Mask = APInt::getAllOnesValue(OpSizeInBits).lshr(ShiftAmt);
/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp839 unsigned ShiftAmt = Shift.getConstantOperandVal(1); local
840 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
845 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
859 AM.Scale = 1 << ShiftAmt;
899 unsigned ShiftAmt = Shift.getConstantOperandVal(1); local
916 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
951 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
/external/llvm/lib/Transforms/Scalar/
H A DGVN.cpp1130 unsigned ShiftAmt; local
1132 ShiftAmt = Offset*8;
1134 ShiftAmt = (StoreSize-LoadSize-Offset)*8;
1136 if (ShiftAmt)
1137 SrcVal = Builder.CreateLShr(SrcVal, ShiftAmt);
/external/clang/lib/CodeGen/
H A DCGBuiltin.cpp1770 int ShiftAmt = cast<ConstantInt>(Shift)->getSExtValue(); local
1777 if (ShiftAmt == EltSize) {
1785 --ShiftAmt;
1786 Shift = ConstantInt::get(VTy->getElementType(), ShiftAmt);
2576 Constant *ShiftAmt = ConstantInt::get(SrcTy->getElementType(), local
2578 ShiftAmt = ConstantVector::getSplat(VTy->getNumElements(), ShiftAmt);
2579 Ops[0] = Builder.CreateLShr(Ops[0], ShiftAmt, "vaddhn");
2887 Constant *ShiftAmt = ConstantInt::get(SrcTy->getElementType(), local
2889 ShiftAmt
4368 uint64_t ShiftAmt = Amt->getZExtValue(); local
4385 uint64_t ShiftAmt = Amt->getZExtValue(); local
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/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp3098 uint32_t ShiftAmt = 0, MaxShiftAmt = IsXReg ? 48 : 16; local
3100 ShiftAmt += 16;
3103 if (ShiftAmt <= MaxShiftAmt && Imm <= 0xFFFF) {
3107 if (ShiftAmt)
3109 ShiftAmt, true, S, E, Ctx));
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1089 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); local
1144 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1149 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1154 .addReg(MaskUpper).addReg(ShiftAmt);
1156 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1215 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1322 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); local
1384 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1389 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1394 .addReg(MaskUpper).addReg(ShiftAmt);
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/external/llvm/lib/Transforms/Utils/
H A DSimplifyCFG.cpp3612 Value *ShiftAmt = Builder.CreateZExtOrTrunc(Index, MapTy, "switch.cast"); local
3615 ShiftAmt = Builder.CreateMul(ShiftAmt,
3620 Value *DownShifted = Builder.CreateLShr(BitMap, ShiftAmt,
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp8054 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt); local
8056 ShiftAmt = ShiftAmt & (32 - 1);
8061 MulAmt >>= ShiftAmt; local
8107 if (ShiftAmt != 0)
8109 Res, DAG.getConstant(ShiftAmt, MVT::i32));
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp968 unsigned ShiftAmt = SVOp->getMaskElt(i); local
969 if (ShiftAmt < i) return -1;
973 ShiftAmt += i;
978 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
983 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
989 ShiftAmt -= i;
994 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
999 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1003 return ShiftAmt;

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