/external/llvm/include/llvm/CodeGen/ |
H A D | DFAPacketizer.h | 76 bool canReserveResources(llvm::MachineInstr *MI); 80 void reserveResources(llvm::MachineInstr *MI); 106 // Generate MI -> SU map. 124 // addToPacket - Add MI to the current packet. 125 virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI) { argument 126 MachineBasicBlock::iterator MII = MI; 127 CurrentPacketMIs.push_back(MI); 128 ResourceTracker->reserveResources(MI); 133 void endPacket(MachineBasicBlock *MBB, MachineInstr *MI); 146 // isSoloInstruction - return true if instruction MI ca 148 isSoloInstruction(MachineInstr *MI) argument [all...] |
/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 31 uint64_t getBinaryCodeForInstr(const MCInst &MI, 35 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, argument
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H A D | R600MCCodeEmitter.cpp | 44 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 49 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 89 void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, argument 92 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 93 if (MI.getOpcode() == AMDGPU::RETURN || 94 MI.getOpcode() == AMDGPU::FETCH_CLAUSE || 95 MI.getOpcode() == AMDGPU::ALU_CLAUSE || 96 MI.getOpcode() == AMDGPU::BUNDLE || 97 MI.getOpcode() == AMDGPU::KILL) { 100 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixup 170 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixup, const MCSubtargetInfo &STI) const argument [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcMCInstLower.cpp | 31 static MCOperand LowerSymbolOperand(const MachineInstr *MI, argument 69 static MCOperand LowerOperand(const MachineInstr *MI, argument 87 return LowerSymbolOperand(MI, MO, AP); 95 void llvm::LowerSparcMachineInstrToMCInst(const MachineInstr *MI, argument 100 OutMI.setOpcode(MI->getOpcode()); 102 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 103 const MachineOperand &MO = MI->getOperand(i); 104 MCOperand MCOp = LowerOperand(MI, MO, AP);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | SIISelLowering.h | 30 void AppendS_WAITCNT(MachineInstr *MI, MachineBasicBlock &BB, 32 void LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB, 34 void LowerSI_INTERP_CONST(MachineInstr *MI, MachineBasicBlock &BB, 36 void LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB, 38 void LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB, 49 virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
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H A D | SIInstrInfo.cpp | 38 MachineBasicBlock::iterator MI, DebugLoc DL, 48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) 55 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc()); local 56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); 57 MachineInstrBuilder(MI).addImm(Imm); 59 return MI; 37 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
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H A D | R600ExpandSpecialInstrs.cpp | 60 MachineInstr &MI = *I; local 63 bool IsReduction = TII->isReductionOp(MI.getOpcode()); 64 bool IsVector = TII->isVector(MI); 65 bool IsCube = TII->isCubeOp(MI.getOpcode()); 96 unsigned DstReg = MI.getOperand(0).getReg(); 97 unsigned Src0 = MI.getOperand(1).getReg(); 102 Src1 = MI.getOperand(2).getReg(); 135 switch (MI.getOpcode()) { 148 Opcode = MI.getOpcode(); 159 MI [all...] |
H A D | R600InstrInfo.cpp | 38 bool R600InstrInfo::isTrig(const MachineInstr &MI) const 40 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG; 43 bool R600InstrInfo::isVector(const MachineInstr &MI) const 45 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR; 50 MachineBasicBlock::iterator MI, DebugLoc DL, 58 BuildMI(MBB, MI, DL, get(AMDGPU::MOV)) 71 BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg) 81 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc()); local 82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); 83 MachineInstrBuilder(MI) 49 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 168 MachineInstr *MI = I; local 251 const MachineInstr *MI = op.getParent(); local 439 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument 455 PredicateInstruction(MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Pred) const argument 470 getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost) const argument 498 addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const argument 505 clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const argument [all...] |
/external/llvm/lib/Target/XCore/InstPrinter/ |
H A D | XCoreInstPrinter.cpp | 32 void XCoreInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 34 printInstruction(MI, O); 39 printInlineJT(const MCInst *MI, int opNum, raw_ostream &O) { argument 44 printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O) { argument 73 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { argument 74 const MCOperand &Op = MI->getOperand(OpNo);
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | SIISelLowering.h | 30 void AppendS_WAITCNT(MachineInstr *MI, MachineBasicBlock &BB, 32 void LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB, 34 void LowerSI_INTERP_CONST(MachineInstr *MI, MachineBasicBlock &BB, 36 void LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB, 38 void LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB, 49 virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
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H A D | SIInstrInfo.cpp | 38 MachineBasicBlock::iterator MI, DebugLoc DL, 48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) 55 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc()); local 56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); 57 MachineInstrBuilder(MI).addImm(Imm); 59 return MI; 37 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
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H A D | R600ExpandSpecialInstrs.cpp | 60 MachineInstr &MI = *I; local 63 bool IsReduction = TII->isReductionOp(MI.getOpcode()); 64 bool IsVector = TII->isVector(MI); 65 bool IsCube = TII->isCubeOp(MI.getOpcode()); 96 unsigned DstReg = MI.getOperand(0).getReg(); 97 unsigned Src0 = MI.getOperand(1).getReg(); 102 Src1 = MI.getOperand(2).getReg(); 135 switch (MI.getOpcode()) { 148 Opcode = MI.getOpcode(); 159 MI [all...] |
H A D | R600InstrInfo.cpp | 38 bool R600InstrInfo::isTrig(const MachineInstr &MI) const 40 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG; 43 bool R600InstrInfo::isVector(const MachineInstr &MI) const 45 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR; 50 MachineBasicBlock::iterator MI, DebugLoc DL, 58 BuildMI(MBB, MI, DL, get(AMDGPU::MOV)) 71 BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg) 81 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc()); local 82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); 83 MachineInstrBuilder(MI) 49 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 168 MachineInstr *MI = I; local 251 const MachineInstr *MI = op.getParent(); local 439 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument 455 PredicateInstruction(MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Pred) const argument 470 getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost) const argument 498 addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const argument 505 clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const argument [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | Mips16ISelLowering.cpp | 165 Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, argument 167 switch (MI->getOpcode()) { 169 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); 171 return emitSel16(Mips::BeqzRxImm16, MI, BB); 173 return emitSel16(Mips::BnezRxImm16, MI, BB); 175 return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB); 177 return emitSeliT16(Mips::Bteqz16, Mips::SltiRxImmX16, MI, BB); 179 return emitSeliT16(Mips::Bteqz16, Mips::SltiuRxImmX16, MI, BB); 181 return emitSeliT16(Mips::Btnez16, Mips::CmpiRxImmX16, MI, BB); 183 return emitSeliT16(Mips::Btnez16, Mips::SltiRxImmX16, MI, B 517 emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const argument 577 emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr *MI, MachineBasicBlock *BB) const argument 641 emitSeliT16(unsigned Opc1, unsigned Opc2, MachineInstr *MI, MachineBasicBlock *BB) const argument 706 emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, MachineInstr *MI, MachineBasicBlock *BB) const argument 722 emitFEXT_T8I8I16_ins( unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned, MachineInstr *MI, MachineBasicBlock *BB) const argument 756 emitFEXT_CCRX16_ins( unsigned SltOpc, MachineInstr *MI, MachineBasicBlock *BB) const argument 773 emitFEXT_CCRXI16_ins( unsigned SltiOpc, unsigned SltiXOpc, MachineInstr *MI, MachineBasicBlock *BB ) const argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | DFAPacketizer.cpp | 91 bool DFAPacketizer::canReserveResources(llvm::MachineInstr *MI) { argument 92 const llvm::MCInstrDesc &MID = MI->getDesc(); 98 void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) { argument 99 const llvm::MCInstrDesc &MID = MI->getDesc(); 148 MachineInstr *MI) { 151 finalizeBundle(*MBB, MIFirst, MI); 167 // Generate MI -> SU map. 176 MachineInstr *MI = BeginItr; local 181 if (this->isSoloInstruction(MI)) { 182 endPacket(MBB, MI); 147 endPacket(MachineBasicBlock *MBB, MachineInstr *MI) argument [all...] |
H A D | InlineSpiller.cpp | 178 bool reMaterializeFor(LiveInterval&, MachineBasicBlock::iterator MI); 181 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg); 184 void insertReload(unsigned VReg, SlotIndex, MachineBasicBlock::iterator MI); 185 void insertSpill(unsigned VReg, bool isKill, MachineBasicBlock::iterator MI); 212 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register, 214 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) { argument 215 if (!MI->isFullCopy()) 217 if (MI->getOperand(0).getReg() == Reg) 218 return MI->getOperand(1).getReg(); 219 if (MI 246 MachineInstr *MI = &*(RI++); local 285 MachineInstr *MI = &*(RI++); local 591 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); local 782 MachineInstr *MI = &*(UI++); local 804 DEBUG(dbgs() << "Redundant spill " << Idx << '\\t' << *MI); local 842 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); local 854 reMaterializeFor(LiveInterval &VirtReg, MachineBasicBlock::iterator MI) argument 866 DEBUG(dbgs() << UseIdx << '\\t' << *MI); local 880 DEBUG(dbgs() << "\\tcannot remat for " << UseIdx << '\\t' << *MI); local 891 DEBUG(dbgs() << "\\tcannot remat tied reg: " << UseIdx << '\\t' << *MI); local 922 DEBUG(dbgs() << "\\t " << UseIdx << '\\t' << *MI << '\\n'); local 945 MachineInstr *MI = &*(RI++); local 961 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); local 1002 coalesceStackAccess(MachineInstr *MI, unsigned Reg) argument 1173 insertReload(unsigned NewVReg, SlotIndex Idx, MachineBasicBlock::iterator MI) argument 1190 insertSpill(unsigned NewVReg, bool isKill, MachineBasicBlock::iterator MI) argument 1214 MachineInstr *MI = &*(RegI++); local 1299 DEBUG(dbgs() << "\\trewrite: " << Idx << '\\t' << *MI << '\\n'); local 1342 MachineInstr *MI = &*(RI++); local [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZShortenInst.cpp | 37 bool shortenIIF(MachineInstr &MI, unsigned *GPRMap, unsigned LiveOther, 70 // MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH 72 // instead of IIxF. If MI loads the high word, GPRMap[X] is the set of high 75 bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned *GPRMap, argument 78 unsigned Reg = MI.getOperand(0).getReg(); 85 uint64_t Imm = MI.getOperand(1).getImm(); 87 MI.setDesc(TII->get(LLIxL)); 88 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); 92 MI.setDesc(TII->get(LLIxH)); 93 MI [all...] |
/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | AsmPrinterInlineAsm.cpp | 158 static void EmitMSInlineAsmStr(const char *AsmStr, const MachineInstr *MI, argument 166 unsigned NumOperands = MI->getNumOperands(); 220 if (OpNo >= MI->getNumOperands()) break; 221 unsigned OpFlags = MI->getOperand(OpNo).getImm(); 228 if (OpNo >= MI->getNumOperands() || 229 MI->getOperand(OpNo).isMetadata()) { 232 unsigned OpFlags = MI->getOperand(OpNo).getImm(); 236 Error = AP->PrintAsmMemoryOperand(MI, OpNo, InlineAsmVariant, 239 Error = AP->PrintAsmOperand(MI, OpNo, InlineAsmVariant, 256 static void EmitGCCInlineAsmStr(const char *AsmStr, const MachineInstr *MI, argument 501 PrintSpecial(const MachineInstr *MI, raw_ostream &OS, const char *Code) const argument 523 << "' for machine instr: " << *MI; local 531 PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument 557 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument [all...] |
/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 145 EncodeInstruction(const MCInst &MI, raw_ostream &OS, 154 MCInst TmpInst = MI; 155 switch (MI.getOpcode()) { 204 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 208 const MCOperand &MO = MI.getOperand(OpNo); 226 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, 230 const MCOperand &MO = MI.getOperand(OpNo); 249 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, 253 const MCOperand &MO = MI.getOperand(OpNo); 271 getBranchTarget26OpValue(const MCInst &MI, unsigne [all...] |
/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 58 bool Is16BitMemOperand(const MCInst &MI, unsigned Op, argument 60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 62 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 88 unsigned char getVEXRegisterEncoding(const MCInst &MI, argument 90 unsigned SrcReg = MI.getOperand(OpNum).getReg(); 91 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum)); 100 unsigned char getWriteMaskRegisterEncoding(const MCInst &MI, argument 102 assert(X86::K0 != MI.getOperand(OpNum).getReg() && 104 unsigned MaskRegNum = GetX86RegNum(MI 385 EmitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField, uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 612 EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, const MCInst &MI, const MCInstrDesc &Desc, raw_ostream &OS) const argument 1012 DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, const MCInstrDesc &Desc) argument 1104 EmitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand, const MCInst &MI, raw_ostream &OS) const argument 1125 EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, const MCInst &MI, const MCInstrDesc &Desc, const MCSubtargetInfo &STI, raw_ostream &OS) const argument 1175 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 64 MachineInstr &MI = *II; local 65 MachineBasicBlock &MBB = *MI.getParent(); 66 DebugLoc dl = MI.getDebugLoc(); 68 switch (MI.getOpcode()) { 73 .addMemOperand(*MI.memoperands_begin()); 77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) 80 .addMemOperand(*MI.memoperands_begin()); 97 MachineInstr &MI = *II; local 98 MachineBasicBlock &MBB = *MI.getParent(); 99 DebugLoc dl = MI 131 MachineInstr &MI = *II; local 165 MachineInstr &MI = *II; local 264 MachineInstr &MI = *II; local [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.cpp | 55 void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 59 unsigned Opcode = MI->getOpcode(); 62 if (printSysAlias(MI, O)) { 70 const MCOperand &Op0 = MI->getOperand(0); 71 const MCOperand &Op1 = MI->getOperand(1); 72 const MCOperand &Op2 = MI->getOperand(2); 73 const MCOperand &Op3 = MI->getOperand(3); 164 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0 165 const MCOperand &Op2 = MI->getOperand(2); 166 int ImmR = MI 616 printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) argument 668 printSysAlias(const MCInst *MI, raw_ostream &O) argument 891 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 905 printHexImm(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 911 printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, raw_ostream &O) argument 924 printVRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 932 printSysCROperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 939 printAddSubImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 960 printLogicalImm32(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 967 printLogicalImm64(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 974 printShifter(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 985 printShiftedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 991 printExtendedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 997 printArithExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1023 printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, char SrcRegKind, unsigned Width) argument 1040 printCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1046 printInverseCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1052 printAMNoIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1058 printImmScale(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1063 printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O) argument 1074 printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O) argument 1087 printPrefetchOp(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1098 printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1153 printVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O, StringRef LayoutSuffix) argument 1196 printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1203 printTypedVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1214 printVectorIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1219 printAlignedLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1243 printAdrpLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument 1258 printBarrierOption(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 1275 printMRSSystemRegister(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 1287 printMSRSystemRegister(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 1299 printSystemPStateField(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 1311 printSIMDType10Operand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | SIInstrInfo.cpp | 37 MachineBasicBlock::iterator MI, DebugLoc DL, 76 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) { 95 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg) 101 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg) 123 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) 161 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL, 186 MachineBasicBlock::iterator MI, 194 DebugLoc DL = MBB.findDebugLoc(MI); 200 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0) 206 BuildMI(MBB, MI, D 36 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 185 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 239 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 296 insertNOPs(MachineBasicBlock::iterator MI, int Count) const argument 368 commuteInstruction(MachineInstr *MI, bool NewMI) const argument 435 isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const argument 544 verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const argument 678 getVALUOp(const MachineInstr &MI) argument 734 getOpRegClass(const MachineInstr &MI, unsigned OpNo) const argument 746 canReadVGPR(const MachineInstr &MI, unsigned OpNo) const argument 758 legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const argument 778 buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const argument 826 split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist, MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineOperand &Op) const argument 1107 moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const argument [all...] |
H A D | R600EmitClauseMarkers.cpp | 40 unsigned OccupiedDwords(MachineInstr *MI) const { 41 switch (MI->getOpcode()) { 55 if (TII->isLDSRetInstr(MI->getOpcode())) 58 if(TII->isVector(*MI) || 59 TII->isCubeOp(MI->getOpcode()) || 60 TII->isReductionOp(MI->getOpcode())) 64 for (MachineInstr::mop_iterator It = MI->operands_begin(), 65 E = MI->operands_end(); It != E; ++It) { 73 bool isALU(const MachineInstr *MI) const { 74 if (TII->isALUInstr(MI 116 SubstituteKCacheBank(MachineInstr *MI, std::vector<std::pair<unsigned, unsigned> > &CachedConsts, bool UpdateInstr = true) const argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 381 MachineInstr &MI = *MBBI; local 382 MachineBasicBlock &MBB = *MI.getParent(); 384 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 389 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 393 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 394 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 406 MIB.addOperand(MI.getOperand(OpIdx++)); 409 MIB.addOperand(MI.getOperand(OpIdx++)); 410 MIB.addOperand(MI.getOperand(OpIdx++)); 413 MIB.addOperand(MI 446 MachineInstr &MI = *MBBI; local 499 MachineInstr &MI = *MBBI; local 589 MachineInstr &MI = *MBBI; local 654 MachineInstr &MI = *MBBI; local 745 MachineInstr &MI = *MBBI; local [all...] |