Searched refs:STI (Results 26 - 50 of 166) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DThumb2RegisterInfo.h26 Thumb2RegisterInfo(const ARMSubtarget &STI);
H A DARMBaseRegisterInfo.cpp47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), BasePtr(ARM::R6) {
48 if (STI.isTargetMachO()) {
49 if (STI.isTargetDarwin() || STI.isThumb1Only())
53 } else if (STI.isTargetWindows())
56 FramePtr = STI.isThumb() ? ARM::R7 : ARM::R11;
61 const MCPhysReg *RegList = (STI.isTargetIOS() && !STI.isAAPCS_ABI())
73 if (STI.isMClass()) {
96 return (STI
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H A DThumb1InstrInfo.cpp23 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) argument
24 : ARMBaseInstrInfo(STI), RI(STI) {
H A DThumb1InstrInfo.h26 explicit Thumb1InstrInfo(const ARMSubtarget &STI);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXFrameLowering.h25 explicit NVPTXFrameLowering(NVPTXSubtarget &STI);
H A DNVPTXFrameLowering.cpp29 NVPTXFrameLowering::NVPTXFrameLowering(NVPTXSubtarget &STI) argument
31 is64bit(STI.is64Bit()) {}
/external/llvm/tools/llvm-mc/
H A DDisassembler.h33 MCSubtargetInfo &STI,
H A DDisassembler.cpp57 const MCSubtargetInfo &STI) {
92 Streamer.EmitInstruction(Inst, STI);
159 MCSubtargetInfo &STI,
181 T.createMCDisassembler(STI, Ctx));
225 InAtomicBlock, STI);
53 PrintInsts(const MCDisassembler &DisAsm, const ByteArrayTy &Bytes, SourceMgr &SM, raw_ostream &Out, MCStreamer &Streamer, bool InAtomicBlock, const MCSubtargetInfo &STI) argument
157 disassemble(const Target &T, const std::string &Triple, MCSubtargetInfo &STI, MCStreamer &Streamer, MemoryBuffer &Buffer, SourceMgr &SM, raw_ostream &Out) argument
/external/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp74 const MCSubtargetInfo &STI);
112 const MCSubtargetInfo &STI)
117 OutStreamer.EmitInstruction(CallInst, STI);
122 const MCSubtargetInfo &STI)
128 OutStreamer.EmitInstruction(SETHIInst, STI);
133 const MCSubtargetInfo &STI)
140 OutStreamer.EmitInstruction(Inst, STI);
145 const MCSubtargetInfo &STI) {
146 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI);
151 const MCSubtargetInfo &STI) {
110 EmitCall(MCStreamer &OutStreamer, MCOperand &Callee, const MCSubtargetInfo &STI) argument
120 EmitSETHI(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument
131 EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI) argument
143 EmitOR(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument
149 EmitADD(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &RS2, MCOperand &RD, const MCSubtargetInfo &STI) argument
155 EmitSHL(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument
162 EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym, SparcMCExpr::VariantKind HiKind, SparcMCExpr::VariantKind LoKind, MCOperand &RD, MCContext &OutContext, const MCSubtargetInfo &STI) argument
175 LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/R600/MCTargetDesc/
H A DR600MCCodeEmitter.cpp46 const MCSubtargetInfo &STI) const override;
51 const MCSubtargetInfo &STI) const override;
85 const MCSubtargetInfo &STI) {
91 const MCSubtargetInfo &STI) const {
100 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
102 if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) {
124 uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI);
134 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
135 if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
173 const MCSubtargetInfo &STI) cons
83 createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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H A DSIMCCodeEmitter.cpp59 const MCSubtargetInfo &STI) const override;
64 const MCSubtargetInfo &STI) const override;
71 const MCSubtargetInfo &STI,
131 const MCSubtargetInfo &STI) const {
133 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
175 const MCSubtargetInfo &STI) const {
69 createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp62 const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(Triple, CPU, local
64 if (!STI)
73 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI, *Ctx);
89 *MAI, *MII, *MRI, *STI);
96 STI, MII, Ctx, DisAsm, IP);
185 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); local
186 InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU());
204 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); local
205 const MCSchedModel *SCModel = STI->getSchedModel();
228 const MCWriteLatencyEntry *WLEntry = STI
334 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); local
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/external/llvm/include/llvm/MC/
H A DMCCodeEmitter.h40 const MCSubtargetInfo &STI) const = 0;
/external/llvm/lib/Target/PowerPC/
H A DPPCJITInfo.h28 PPCJITInfo(PPCSubtarget &STI);
/external/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.h98 X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
/external/llvm/lib/CodeGen/
H A DLLVMTargetMachine.cpp171 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); local
178 MII, MRI, STI);
183 MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, *Context);
197 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, STI,
205 getTargetTriple(), *Context, *MAB, Out, MCE, STI, local
269 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); local
271 STI, *Ctx);
279 getTargetTriple(), *Ctx, *MAB, Out, MCE, STI, local
H A DTargetSchedule.cpp58 STI = sti;
60 STI->initInstrItins(InstrItins);
117 SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
193 STI->getWriteLatencyEntry(SCDesc, DefIdx);
204 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
245 STI->getWriteLatencyEntry(SCDesc, DefIdx);
280 for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
281 *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCTargetDesc.h38 const MCSubtargetInfo &STI,
42 const MCSubtargetInfo &STI,
/external/llvm/lib/Target/Sparc/InstPrinter/
H A DSparcInstPrinter.h25 const MCSubtargetInfo &STI; member in class:llvm::SparcInstPrinter
31 : MCInstPrinter(MAI, MII, MRI), STI(sti) {}
/external/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp38 : AArch64GenRegisterInfo(AArch64::LR), TII(tii), STI(sti) {}
58 if (STI->isTargetDarwin())
61 assert(STI->isTargetELF() && "only expect Darwin or ELF TLS");
88 if (TFI->hasFP(MF) || STI->isTargetDarwin()) {
93 if (STI->isTargetDarwin()) {
120 return STI->isTargetDarwin();
123 return TFI->hasFP(MF) || STI->isTargetDarwin();
381 - (TFI->hasFP(MF) || STI->isTargetDarwin()) // FP
382 - STI->isTargetDarwin() // X18 reserved as platform register
/external/llvm/include/llvm/Support/
H A DTargetRegistry.h109 MCSubtargetInfo &STI,
114 const MCSubtargetInfo &STI,
121 const MCSubtargetInfo &STI);
124 const MCSubtargetInfo &STI,
132 const MCSubtargetInfo &STI,
373 MCSubtargetInfo &STI,
379 return MCAsmParserCtorFn(STI, Parser, MII, Options);
390 MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI, argument
394 return MCDisassemblerCtorFn(*this, STI, Ctx);
401 const MCSubtargetInfo &STI) cons
372 createMCAsmParser( MCSubtargetInfo &STI, MCAsmParser &Parser, const MCInstrInfo &MII, const MCTargetOptions &Options) const argument
409 createMCCodeEmitter(const MCInstrInfo &II, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) const argument
427 createMCObjectStreamer(StringRef TT, MCContext &Ctx, MCAsmBackend &TAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) const argument
1110 Allocator(MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII, const MCTargetOptions &Options) argument
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/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.h39 const MCSubtargetInfo &STI,
/external/llvm/lib/Target/Mips/
H A DMips16FrameLowering.h22 explicit Mips16FrameLowering(const MipsSubtarget &STI);
H A DMipsSEFrameLowering.h23 explicit MipsSEFrameLowering(const MipsSubtarget &STI);
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.h40 const MCSubtargetInfo &STI,

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