Searched refs:isReg (Results 76 - 100 of 180) sorted by relevance

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/external/llvm/lib/Target/R600/MCTargetDesc/
H A DSIMCCodeEmitter.cpp176 if (MO.isReg())
H A DR600MCCodeEmitter.cpp174 if (MO.isReg()) {
/external/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp132 if (MO.isReg()) {
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUInstrInfo.cpp247 if (MO.isReg() && MO.isDef()) {
/external/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp318 if (Src.isReg()) {
330 } else if (Src.isReg()) {
/external/llvm/lib/Target/R600/
H A DAMDGPUAsmPrinter.cpp167 if (!MO.isReg())
237 if (!MO.isReg()) {
H A DR600MachineScheduler.cpp164 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
368 if (MO.isReg() && !MO.isDef() &&
/external/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp242 assert(Inst.getOperand(0).isReg() &&
244 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
296 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
300 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
301 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
303 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
304 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
/external/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp213 if (MI->getOperand(OpNum).isReg()) {
230 if (MI->getOperand(OpNum).isReg()) {
255 if (!MI->getOperand(OpNum).isReg())
276 while (MI->getOperand(RegOps).isReg()) {
318 if (!MO.isReg())
332 if (!MO.isReg())
341 if (!MI->getOperand(OpNum).isReg())
358 if (!MO.isReg())
388 if (!MI->getOperand(OpNum).isReg())
396 assert(MO.isReg()
[all...]
H A DARMCodeEmitter.cpp249 if (!MO.isReg()) {
287 if (!MO.isReg()) {
444 if (MO.isReg())
993 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
1085 if (MO.isReg()) {
1291 if (!MO.isReg() || MO.isImplicit())
1355 if (MO2.isReg()) {
1701 if (Base.isReg()) {
1752 if (!MO.isReg() || MO.isImplicit())
H A DThumb2ITBlockPass.cpp65 if (!MO.isReg())
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp771 if (MO.isReg()) {
1029 if (!MO.isReg()) continue;
1040 if (MI.getOperand(0).isReg() &&
1046 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1051 if (MI.getOperand(0).isReg() &&
1058 if (MO.isReg()) {
1074 if (NumOps > e && MI.getOperand(e).isReg() &&
1080 if (MO.isReg()) {
1089 if (MI.getOperand(0).isReg() &&
1095 if (MO.isReg()
[all...]
/external/llvm/lib/CodeGen/
H A DMachineVerifier.cpp768 if (!MO.isReg() || !MO.isImplicit())
823 if (!MO->isReg())
833 if (MO->isReg() &&
843 if (!MO->isReg())
849 } else if (MO->isReg() && MO->isTied())
853 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
869 if (!OtherMO.isReg())
1401 if (!MOI->isReg() || !MOI->isDef())
1523 if (!MOI->isReg() || MOI->getReg() != Reg)
H A DMachineRegisterInfo.cpp146 if (!MO->isReg()) {
259 if (Src->isReg()) {
H A DVirtRegMap.cpp330 if (MO.isReg() && MO.getReg())
336 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
H A DLiveVariables.cpp216 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
570 if (!MO.isReg() || MO.getReg() == 0)
687 if (MO.isReg() && MO.isKill()) {
803 if (I->isReg() && TargetRegisterInfo::isVirtualRegister(I->getReg())) {
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp512 if (MO.isReg()) {
670 if (MCOp1.isImm() && MCOp2.isReg() &&
870 if (!MO.isReg()) {
954 if (!MO.isReg()) {
1113 bool isReg = MO.getReg() != 0; local
1116 if (isReg) {
1122 return Binary | (isAdd << 12) | (isReg << 13);
1171 if (!MO.isReg()) {
1247 if (!MO.isReg()) {
/external/llvm/utils/TableGen/
H A DFastISelEmitter.cpp94 bool isReg() const { return Repr == OK_Reg; }
102 if (isReg())
285 if (Operands[i].isReg()) {
310 if (Operands[i].isReg()) {
327 if (Operands[i].isReg()) {
H A DFixedLenDecoderEmitter.cpp1855 bool isReg = false;
1860 isReg = true;
1864 isReg = true;
1870 if (!isReg && String && String->getValue() != "")
1927 bool isReg = false;
1932 isReg = true;
1936 isReg = true;
1942 if (!isReg && String && String->getValue() != "")
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp302 if (Op.isReg()) {
465 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
566 if (!MO1.isReg()) { // For label symbolic references.
642 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
995 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1016 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1079 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1143 if (!MO1.isReg()) { // For label symbolic references.
/external/llvm/lib/Target/Mips/
H A DMipsCodeEmitter.cpp241 assert(MI.getOperand(OpNo).isReg());
293 if (MO.isReg())
H A DMipsInstrInfo.cpp106 if (Cond[i].isReg())
H A DMipsSEFrameLowering.cpp127 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
147 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
170 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
200 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
/external/llvm/lib/Target/Hexagon/InstPrinter/
H A DHexagonInstPrinter.cpp93 if (MO.isReg()) {
/external/llvm/lib/Target/NVPTX/InstPrinter/
H A DNVPTXInstPrinter.cpp85 if (Op.isReg()) {

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