Searched refs:TII (Results 101 - 125 of 224) sorted by relevance

123456789

/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIAssignInterpRegs.cpp126 const TargetInstrInfo * TII = TM.getInstrInfo(); local
131 TII->get(TargetOpcode::COPY), virtReg)
H A DSIISelLowering.h24 const SIInstrInfo * TII; member in class:llvm::SITargetLowering
/external/llvm/lib/Target/ARM/
H A DARMConstantIslandPass.cpp260 const ARMBaseInstrInfo *TII; member in class:__anon25967::ARMConstantIslands
385 TII = (const ARMBaseInstrInfo*)MF->getTarget().getInstrInfo();
546 BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
807 BBI.Size += TII->GetInstSizeInBytes(I);
838 Offset += TII->GetInstSizeInBytes(I);
891 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
893 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB)
1261 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1263 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB)
1322 for (unsigned Offset = UserOffset+TII
[all...]
H A DMLxExpansionPass.cpp51 const ARMBaseInstrInfo *TII; member in struct:__anon26004::MLxExpansion
221 if (TII->isFpMLxInstruction(DefMI->getOpcode())) {
256 if (TII->canCauseFpMLxStall(NextMI->getOpcode())) {
287 const MCInstrDesc &MCID1 = TII->get(MulOpc);
288 const MCInstrDesc &MCID2 = TII->get(AddSubOpc);
291 TII->getRegClass(MCID1, 0, TRI, MF));
362 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
381 TII = static_cast<const ARMBaseInstrInfo*>(Fn.getTarget().getInstrInfo());
H A DThumb1RegisterInfo.h49 const ARMBaseInstrInfo &TII) const;
H A DARMExpandPseudoInsts.cpp46 const ARMBaseInstrInfo *TII; member in class:__anon25968::ARMExpandPseudo
390 TII->get(TableEntry->RealOpc));
455 TII->get(TableEntry->RealOpc));
509 TII->get(TableEntry->RealOpc));
592 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
671 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
672 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
701 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
702 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
753 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII
[all...]
H A DARMLoadStoreOptimizer.cpp68 const TargetInstrInfo *TII; member in struct:__anon25980::ARMLoadStoreOpt
134 const TargetInstrInfo *TII,
386 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII->get(ARM::tSUBi8), Base))
404 AddDefaultT1CC(BuildMI(MBB, --MBBI, dl, TII->get(ARM::tSUBi8), Base))
479 BuildMI(MBB, MBBI, dl, TII->get(ARM::tMOVr), NewBase)
483 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase))
487 BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase)
522 MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode));
535 MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode));
1053 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII
1121 MergeBaseUpdateLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const TargetInstrInfo *TII, bool &Advance, MachineBasicBlock::iterator &I) argument
1358 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument
1767 const TargetInstrInfo *TII; member in struct:__anon25981::ARMPreAllocLoadStoreOpt
[all...]
/external/llvm/lib/Target/R600/
H A DR600OptimizeVectorRegisters.cpp87 const R600InstrInfo *TII; member in class:__anon26117::R600VectorRegMerger
111 TII(nullptr) { }
133 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
195 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG),
212 Pos = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg)
249 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
317 TII = static_cast<const R600InstrInfo *>(Fn.getTarget().getInstrInfo());
330 if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
H A DSIRegisterInfo.cpp30 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo()); local
31 TII->reserveIndirectRegisters(Reserved, MF);
H A DSIISelLowering.cpp283 const SIInstrInfo *TII = local
285 return TII->isInlineConstant(Imm);
461 const SIInstrInfo *TII = local
475 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
477 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
479 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
481 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
486 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
496 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg)
512 BuildMI(*BB, I, MI->getDebugLoc(), TII
522 const SIInstrInfo *TII = local
537 const SIInstrInfo *TII = local
551 const SIInstrInfo *TII = local
1230 const SIInstrInfo *TII = local
1265 const SIInstrInfo *TII = local
1374 const SIInstrInfo *TII = local
1638 const SIInstrInfo *TII = local
1652 const SIInstrInfo *TII = local
[all...]
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIAssignInterpRegs.cpp126 const TargetInstrInfo * TII = TM.getInstrInfo(); local
131 TII->get(TargetOpcode::COPY), virtReg)
H A DSIISelLowering.h24 const SIInstrInfo * TII; member in class:llvm::SITargetLowering
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp132 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
176 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
221 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
293 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
331 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
335 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
455 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
493 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
503 TII
[all...]
H A DScheduleDAGRRList.cpp278 const TargetInstrInfo *TII,
308 const MCInstrDesc Desc = TII->get(Opcode);
309 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
410 const TargetInstrInfo *TII) {
420 if (IsChainDependent(N->getOperand(i).getNode(), Inner, NestLevel, TII))
427 (unsigned)TII->getCallFrameDestroyOpcode()) {
430 (unsigned)TII->getCallFrameSetupOpcode()) {
460 const TargetInstrInfo *TII) {
472 MyNestLevel, MyMaxNest, TII))
485 (unsigned)TII
276 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF) argument
408 IsChainDependent(SDNode *Outer, SDNode *Inner, unsigned NestLevel, const TargetInstrInfo *TII) argument
459 FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest, const TargetInstrInfo *TII) argument
1192 getPhysicalRegisterVT(SDNode *N, unsigned Reg, const TargetInstrInfo *TII) argument
[all...]
/external/llvm/lib/CodeGen/
H A DEarlyIfConversion.cpp82 const TargetInstrInfo *TII; member in class:__anon25739::SSAIfConv
156 TII = MF.getTarget().getInstrInfo();
223 if (!I->isSafeToMove(TII, nullptr, DontMoveAcrossStore)) {
389 if (TII->AnalyzeBranch(*Head, TBB, FBB, Cond)) {
423 if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg,
464 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
485 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
541 TII->RemoveBranch(*Head);
568 TII->InsertBranch(*Head, Tail, nullptr, EmptyCond, HeadDL);
581 const TargetInstrInfo *TII; member in class:__anon25740::EarlyIfConverter
[all...]
H A DCriticalAntiDepBreaker.h37 const TargetInstrInfo *TII; member in class:llvm::CriticalAntiDepBreaker
H A DLiveRangeEdit.cpp56 if (!TII.isTriviallyReMaterializable(DefMI, aa))
138 if (cheapAsAMove && !TII.isAsCheapAsAMove(RM.OrigMI))
155 TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
201 if (!DefMI->isSafeToMove(&TII, nullptr, SawStore))
211 MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI);
240 if (!MI->isSafeToMove(&TII, nullptr, SawStore)) {
303 MI->setDesc(TII.get(TargetOpcode::KILL));
H A DTwoAddressInstructionPass.cpp72 const TargetInstrInfo *TII; member in class:__anon25830::TwoAddressInstructionPass
188 if (!MI->isSafeToMove(TII, AA, SeenStore))
338 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, argument
403 const TargetInstrInfo *TII,
426 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
453 const TargetInstrInfo *TII,
464 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
578 MachineInstr *NewMI = TII->commuteInstruction(MI);
626 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV);
667 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCop
401 isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives) argument
451 findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys) argument
[all...]
H A DExecutionDepsFix.cpp133 const TargetInstrInfo *TII; member in class:__anon25744::ExeDepsFix
311 TII->setExecutionDomain(dv->Instrs.pop_back_val(), domain);
452 std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(MI);
500 unsigned Pref = TII->getUndefRegClearance(MI, OpNum, TRI);
526 unsigned Pref = TII->getPartialRegUpdateClearance(MI, i, TRI);
528 TII->breakPartialRegDependency(MI, i, TRI);
564 TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);
637 TII->setExecutionDomain(mi, domain);
716 TII = MF->getTarget().getInstrInfo();
H A DTailDuplication.cpp63 const TargetInstrInfo *TII; member in class:__anon25829::TailDuplicatePass
138 TII = MF.getTarget().getInstrInfo();
432 MachineInstr *NewMI = TII->duplicate(MI, MF);
660 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
691 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
729 TII->RemoveBranch(*PredBB);
732 TII->InsertBranch(*PredBB, PredTBB, PredFBB, PredCond, DebugLoc());
780 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
794 TII->RemoveBranch(*PredBB);
835 TII
[all...]
H A DMachineSink.cpp47 const TargetInstrInfo *TII; member in class:__anon25775::MachineSinking
217 TII = TM.getInstrInfo();
295 if (!MI->isCopy() && !TII->isAsCheapAsAMove(MI))
512 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
595 if (!MI->isSafeToMove(TII, AA, SawStore))
636 if (!MI->isSafeToMove(TII, AA, store)) {
/external/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp194 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo(); local
242 if (TII->isSchedulingBoundary(std::prev(I), MBB, Fn))
276 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
292 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
306 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
326 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
406 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
414 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
437 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
450 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
[all...]
/external/llvm/include/llvm/CodeGen/
H A DMachineSSAUpdater.h54 const TargetInstrInfo *TII; member in class:llvm::MachineSSAUpdater
/external/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp134 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
136 MI.setDesc(TII.get(MSP430::MOV16rr));
145 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
148 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2598 const SystemZInstrInfo *TII) {
2607 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
2616 const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>( local
2634 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2648 BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
2665 const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>( local
2676 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
2684 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
2703 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2712 BuildMI(MBB, DL, TII
2597 forceReg(MachineInstr *MI, MachineOperand &Base, const SystemZInstrInfo *TII) argument
2734 const SystemZInstrInfo *TII = local
2858 const SystemZInstrInfo *TII = local
2970 const SystemZInstrInfo *TII = local
3087 const SystemZInstrInfo *TII = local
3119 const SystemZInstrInfo *TII = local
3289 const SystemZInstrInfo *TII = local
[all...]

Completed in 1983 milliseconds

123456789