/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 255 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { argument 303 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 307 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 312 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 316 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 321 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 325 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 329 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 499 const PPCInstrInfo &TII = local 523 HandleVRSaveUpdate(MBBI, TII); 814 const PPCInstrInfo &TII = local 1370 const PPCInstrInfo &TII = local 1432 const PPCInstrInfo &TII = local 1465 const PPCInstrInfo &TII = local 1515 const PPCInstrInfo &TII = local [all...] |
H A D | PPCFastISel.cpp | 87 const TargetInstrInfo &TII; member in class:__anon26084::final 97 TII(*TM.getInstrInfo()), 408 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8), 500 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) 506 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) 530 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) 616 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) 624 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) 644 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) 708 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII [all...] |
H A D | PPCISelDAGToDAG.cpp | 235 const TargetInstrInfo &TII = *TM.getInstrInfo(); local 243 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); 244 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), 246 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); 260 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); 271 const TargetInstrInfo &TII = *TM.getInstrInfo(); local 279 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); 280 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); 283 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8)); 284 BuildMI(FirstMBB, MBBI, dl, TII [all...] |
H A D | PPCInstrInfo.cpp | 99 assert(DAG->TII && "No InstrInfo?"); 1613 const PPCInstrInfo *TII; member in struct:__anon26090::PPCVSXFMAMutate 1763 MI->setDesc(TII->get(AltOpc)); 1830 TII = TM->getInstrInfo(); 1887 const PPCInstrInfo *TII; member in struct:__anon26091::PPCVSXCopy 1940 TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg) 1964 TII->get(TargetOpcode::COPY), NewVReg) 1983 TII = TM->getInstrInfo(); 2027 const PPCInstrInfo *TII; member in struct:__anon26092::PPCVSXCopyCleanup 2060 TII 2106 const PPCInstrInfo *TII; member in struct:__anon26093::PPCEarlyReturn [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 679 const SystemZInstrInfo *TII = getInstrInfo(); local 683 if (TII->isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) {
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/external/llvm/lib/CodeGen/ |
H A D | IfConversion.cpp | 162 const TargetInstrInfo *TII; member in class:__anon25750::IfConverter 219 return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra, 229 TII->isProfitableToIfCvt(TBB, TCycle, TExtra, FBB, FCycle, FExtra, 273 TII = MF.getTarget().getInstrInfo(); 280 SchedModel.init(*ST.getSchedModel(), &ST, TII); 282 if (!TII) return false; 290 BFChange = BF.OptimizeFunction(MF, TII, 424 BF.OptimizeFunction(MF, TII, 450 if (!TII->ReverseBranchCondition(BBI.BrCond)) { 451 TII 955 InsertUncondBranch(MachineBasicBlock *BB, MachineBasicBlock *ToBB, const TargetInstrInfo *TII) argument 1504 MaySpeculate(const MachineInstr *MI, SmallSet<unsigned, 4> &LaterRedefs, const TargetInstrInfo *TII) argument [all...] |
H A D | MachineInstr.cpp | 969 const TargetInstrInfo *TII, 977 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); 1005 unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, 1013 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI); 1018 CurRC, TII, TRI); 1024 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const { 1031 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI); 1036 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const { 1037 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); 1293 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, argument 1004 getRegClassConstraintEffectForVReg( unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle) const argument 1022 getRegClassConstraintEffectForVRegImpl( unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const argument 1034 getRegClassConstraintEffect( unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const argument [all...] |
H A D | MachineVerifier.cpp | 68 const TargetInstrInfo *TII; member in struct:__anon25778::MachineVerifier 295 TII = TM->getInstrInfo(); 557 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB), 581 !TII->isPredicated(&MBB->back())) { 720 if (MI->isTerminator() && !TII->isPredicated(MI)) { 811 if (!TII->verifyInstruction(MI, ErrorInfo)) 904 TII->getRegClass(MCID, MONum, TRI, *MF)) { 931 TII->getRegClass(MCID, MONum, TRI, *MF)) { 1644 int FrameSetupOpcode = TII->getCallFrameSetupOpcode(); 1645 int FrameDestroyOpcode = TII [all...] |
H A D | RegAllocGreedy.cpp | 111 const TargetInstrInfo *TII; member in class:__anon25792::RAGreedy 1497 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, 1502 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, 1545 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII, 2324 TII = TM.getInstrInfo(); 1495 getNumAllocatableRegsForConstraints( const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, const RegisterClassInfo &RCI) argument
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H A D | RegisterCoalescer.cpp | 83 const TargetInstrInfo* TII; member in class:__anon25794::RegisterCoalescer 603 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) 642 MachineInstr *NewMI = TII->commuteInstruction(DefMI); 754 if (!TII->isAsCheapAsAMove(DefMI)) 756 if (!TII->isTriviallyReMaterializable(DefMI, AA)) 759 if (!DefMI->isSafeToMove(TII, AA, SawStore)) 778 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); 803 TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, DefMI, *TRI); 2212 TII = TM->getInstrInfo();
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H A D | MachineScheduler.cpp | 374 const TargetInstrInfo *TII, 376 return MI->isCall() || TII->isSchedulingBoundary(MI, MBB, *MF); 381 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); local 420 isSchedBoundary(std::prev(RegionEnd), MBB, MF, TII, IsPostRA)) { 431 if (isSchedBoundary(std::prev(I), MBB, MF, TII, IsPostRA)) 1234 const TargetInstrInfo *TII; member in class:__anon25770::LoadClusterMutation 1239 : TII(tii), TRI(tri) {} 1254 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI)) 1269 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength) 1332 const TargetInstrInfo *TII; member in class:__anon25771::MacroFusion 371 isSchedBoundary(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB, MachineFunction *MF, const TargetInstrInfo *TII, bool IsPostRA) argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGRRList.cpp | 278 const TargetInstrInfo *TII, 308 const MCInstrDesc Desc = TII->get(Opcode); 309 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF); 410 const TargetInstrInfo *TII) { 420 if (IsChainDependent(N->getOperand(i).getNode(), Inner, NestLevel, TII)) 427 (unsigned)TII->getCallFrameDestroyOpcode()) { 430 (unsigned)TII->getCallFrameSetupOpcode()) { 460 const TargetInstrInfo *TII) { 472 MyNestLevel, MyMaxNest, TII)) 485 (unsigned)TII 276 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF) argument 408 IsChainDependent(SDNode *Outer, SDNode *Inner, unsigned NestLevel, const TargetInstrInfo *TII) argument 459 FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest, const TargetInstrInfo *TII) argument 1192 getPhysicalRegisterVT(SDNode *N, unsigned Reg, const TargetInstrInfo *TII) argument [all...] |
H A D | SelectionDAGISel.cpp | 414 const TargetInstrInfo &TII = *TM.getInstrInfo(); local 457 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 498 TII.get(TargetOpcode::DBG_VALUE), 520 TII.get(TargetOpcode::DBG_VALUE), 3263 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 3264 Msg << "target intrinsic %" << TII->getName(iid);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMConstantIslandPass.cpp | 260 const ARMBaseInstrInfo *TII; member in class:__anon25967::ARMConstantIslands 385 TII = (const ARMBaseInstrInfo*)MF->getTarget().getInstrInfo(); 546 BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY)) 807 BBI.Size += TII->GetInstSizeInBytes(I); 838 Offset += TII->GetInstSizeInBytes(I); 891 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB); 893 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB) 1261 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB); 1263 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB) 1322 for (unsigned Offset = UserOffset+TII [all...] |
H A D | ARMFrameLowering.cpp | 93 const ARMBaseInstrInfo &TII, 116 const ARMBaseInstrInfo &TII, unsigned DestReg, 123 Pred, PredReg, TII, MIFlags); 126 Pred, PredReg, TII, MIFlags); 131 const ARMBaseInstrInfo &TII, int NumBytes, 135 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, 168 const ARMBaseInstrInfo &TII = local 194 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize, 199 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 206 emitSPUpdate(isARM, MBB, MBBI, dl, TII, 92 isCSRestore(MachineInstr *MI, const ARMBaseInstrInfo &TII, const MCPhysReg *CSRegs) argument 114 emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, const ARMBaseInstrInfo &TII, unsigned DestReg, unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags, ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) argument 129 emitSPUpdate(bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, const ARMBaseInstrInfo &TII, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags, ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) argument 578 const ARMBaseInstrInfo &TII = local 806 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 879 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 969 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 1128 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 1261 GetFunctionSizeInBytes(const MachineFunction &MF, const ARMBaseInstrInfo &TII) argument 1389 const ARMBaseInstrInfo &TII = local 1630 const ARMBaseInstrInfo &TII = local 1748 const ARMBaseInstrInfo &TII = local [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 68 const TargetInstrInfo *TII; member in struct:__anon25980::ARMLoadStoreOpt 134 const TargetInstrInfo *TII, 386 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII->get(ARM::tSUBi8), Base)) 404 AddDefaultT1CC(BuildMI(MBB, --MBBI, dl, TII->get(ARM::tSUBi8), Base)) 479 BuildMI(MBB, MBBI, dl, TII->get(ARM::tMOVr), NewBase) 483 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase)) 487 BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase) 522 MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode)); 535 MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode)); 1053 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII 1121 MergeBaseUpdateLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const TargetInstrInfo *TII, bool &Advance, MachineBasicBlock::iterator &I) argument 1358 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument 1767 const TargetInstrInfo *TII; member in struct:__anon25981::ARMPreAllocLoadStoreOpt [all...] |
H A D | ARMFastISel.cpp | 84 const TargetInstrInfo &TII; member in class:__anon25970::final 98 TII(*TM.getInstrInfo()), 290 const MCInstrDesc &II = TII.get(MachineInstOpcode); 302 TII.get(TargetOpcode::COPY), ResultReg) 313 const MCInstrDesc &II = TII.get(MachineInstOpcode); 330 TII.get(TargetOpcode::COPY), ResultReg) 342 const MCInstrDesc &II = TII.get(MachineInstOpcode); 362 TII.get(TargetOpcode::COPY), ResultReg) 373 const MCInstrDesc &II = TII.get(MachineInstOpcode); 388 TII [all...] |
H A D | ARMISelDAGToDAG.cpp | 427 const ARMBaseInstrInfo *TII = static_cast<const ARMBaseInstrInfo *>( local 430 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode()); 449 return TII->isFpMLxInstruction(Opcode);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 68 const HexagonInstrInfo *TII; member in struct:__anon26012::HexagonHardwareLoops 305 TII = static_cast<const HexagonInstrInfo*>(TM->getInstrInfo()); 374 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false); 388 bool CmpAnalyzed = TII->analyzeCompare(PredI, CmpReg1, CmpReg2, 482 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false); 506 bool AnalyzedCmp = TII->analyzeCompare(CondI, CmpReg1, CmpReg2, 781 const MCInstrDesc &SubD = RegToReg ? TII->get(Hexagon::SUB_rr) : 782 (RegToImm ? TII->get(Hexagon::SUB_ri) : 783 TII->get(Hexagon::ADD_ri)); 811 const MCInstrDesc &AddD = TII [all...] |
H A D | HexagonISelDAGToDAG.cpp | 449 const HexagonInstrInfo *TII = local 451 if (TII->isValidAutoIncImm(LoadedVT, Val)) { 516 const HexagonInstrInfo *TII = local 518 if (TII->isValidAutoIncImm(LoadedVT, Val)) { 594 const HexagonInstrInfo *TII = local 597 if (TII->isValidAutoIncImm(LoadedVT, Val)) 602 if (TII->isValidAutoIncImm(LoadedVT, Val)) 607 if (TII->isValidAutoIncImm(LoadedVT, Val)) 612 if (TII->isValidAutoIncImm(LoadedVT, Val)) 629 if (TII 704 const HexagonInstrInfo *TII = local 1221 const HexagonInstrInfo *TII = local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsConstantIslandPass.cpp | 348 const Mips16InstrInfo *TII; member in class:__anon26048::MipsConstantIslands 458 TII = (const Mips16InstrInfo*)MF->getTarget().getInstrInfo(); 580 BuildMI(*BB, InsAt, DebugLoc(), TII->get(Mips::CONSTPOOL_ENTRY)) 822 BBI.Size += TII->GetInstSizeInBytes(I); 840 Offset += TII->GetInstSizeInBytes(I); 896 BuildMI(OrigBB, DebugLoc(), TII->get(Mips::Bimm16)).addMBB(NewBB); 1144 UserMI->setDesc(TII->get(U.getLongFormOpcode())); 1275 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB); 1319 for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI); 1321 Offset += TII [all...] |
/external/llvm/lib/Target/R600/ |
H A D | AMDILCFGStructurizer.cpp | 138 MachineFunctionPass(ID), TII(nullptr), TRI(nullptr) { 163 TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo()); 164 TRI = &TII->getRegisterInfo(); 184 const R600InstrInfo *TII; member in class:__anon26106::AMDGPUCFGStructurizer 471 ->CreateMachineInstr(TII->get(NewOpcode), DL); 480 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); 494 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DebugLoc()); 506 MachineInstr *NewMI = MF->CreateMachineInstr(TII->get(NewOpcode), DL); 518 MachineInstr *NewInstr = MF->CreateMachineInstr(TII->get(NewOpcode), DL); 529 MF->CreateMachineInstr(TII [all...] |
H A D | R600ISelLowering.cpp | 191 const R600InstrInfo *TII = local 198 if (TII->isLDSRetInstr(MI->getOpcode())) { 199 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst); 206 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode()))); 215 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I, 219 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP); 224 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I, 228 TII->addFlag(NewMI, 0, MO_FLAG_ABS); 233 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I, 237 TII 645 const R600InstrInfo *TII = local 2055 const R600InstrInfo *TII = local 2180 const R600InstrInfo *TII = local [all...] |
H A D | SIISelLowering.cpp | 283 const SIInstrInfo *TII = local 285 return TII->isInlineConstant(Imm); 461 const SIInstrInfo *TII = local 475 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo) 477 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo) 479 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi) 481 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi) 486 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg) 496 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg) 512 BuildMI(*BB, I, MI->getDebugLoc(), TII 522 const SIInstrInfo *TII = local 537 const SIInstrInfo *TII = local 551 const SIInstrInfo *TII = local 1230 const SIInstrInfo *TII = local 1265 const SIInstrInfo *TII = local 1374 const SIInstrInfo *TII = local 1638 const SIInstrInfo *TII = local 1652 const SIInstrInfo *TII = local [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1544 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); local 1579 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)) 1595 TII.get(XCore::PHI), MI->getOperand(0).getReg())
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